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[RISCV][GISel] Promote s32 constant shift amounts to s64 on RV64.
This allows us to reuse isel patterns from SelectionDAG. This is similar to what is done on AArch64.
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16 files changed

+308
-232
lines changed

16 files changed

+308
-232
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 36 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
#include "RISCVLegalizerInfo.h"
1414
#include "RISCVSubtarget.h"
1515
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16+
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
17+
#include "llvm/CodeGen/MachineRegisterInfo.h"
1618
#include "llvm/CodeGen/TargetOpcodes.h"
1719
#include "llvm/CodeGen/ValueTypes.h"
1820
#include "llvm/IR/DerivedTypes.h"
@@ -44,7 +46,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
4446
getActionDefinitionsBuilder({G_SADDO, G_SSUBO}).minScalar(0, sXLen).lower();
4547

4648
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
47-
.legalFor({{s32, s32}, {sXLen, sXLen}})
49+
.customIf([=, &ST](const LegalityQuery &Query) {
50+
return ST.is64Bit() && typeIs(0, s32)(Query) && typeIs(1, s32)(Query);
51+
})
52+
.legalFor({{s32, s32}, {s32, sXLen}, {sXLen, sXLen}})
4853
.widenScalarToNextPow2(0)
4954
.clampScalar(1, s32, sXLen)
5055
.clampScalar(0, s32, sXLen)
@@ -256,12 +261,42 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
256261
getLegacyLegalizerInfo().computeTables();
257262
}
258263

264+
bool RISCVLegalizerInfo::legalizeShlAshrLshr(
265+
MachineInstr &MI, MachineIRBuilder &MIRBuilder,
266+
GISelChangeObserver &Observer) const {
267+
assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
268+
MI.getOpcode() == TargetOpcode::G_LSHR ||
269+
MI.getOpcode() == TargetOpcode::G_SHL);
270+
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
271+
// If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
272+
// imported patterns can select it later. Either way, it will be legal.
273+
Register AmtReg = MI.getOperand(2).getReg();
274+
auto VRegAndVal = getIConstantVRegValWithLookThrough(AmtReg, MRI);
275+
if (!VRegAndVal)
276+
return true;
277+
// Check the shift amount is in range for an immediate form.
278+
uint64_t Amount = VRegAndVal->Value.getZExtValue();
279+
if (Amount > 31)
280+
return true; // This will have to remain a register variant.
281+
auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
282+
Observer.changingInstr(MI);
283+
MI.getOperand(2).setReg(ExtCst.getReg(0));
284+
Observer.changedInstr(MI);
285+
return true;
286+
}
287+
259288
bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
260289
MachineInstr &MI) const {
290+
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
291+
GISelChangeObserver &Observer = Helper.Observer;
261292
switch (MI.getOpcode()) {
262293
default:
263294
// No idea what to do.
264295
return false;
296+
case TargetOpcode::G_SHL:
297+
case TargetOpcode::G_ASHR:
298+
case TargetOpcode::G_LSHR:
299+
return legalizeShlAshrLshr(MI, MIRBuilder, Observer);
265300
case TargetOpcode::G_SEXT_INREG: {
266301
// Source size of 32 is sext.w.
267302
int64_t SizeInBits = MI.getOperand(2).getImm();

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717

1818
namespace llvm {
1919

20+
class GISelChangeObserver;
21+
class MachineIRBuilder;
2022
class RISCVSubtarget;
2123

2224
/// This class provides the information for the target register banks.
@@ -25,6 +27,10 @@ class RISCVLegalizerInfo : public LegalizerInfo {
2527
RISCVLegalizerInfo(const RISCVSubtarget &ST);
2628

2729
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
30+
31+
private:
32+
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
33+
GISelChangeObserver &Observer) const;
2834
};
2935
} // end namespace llvm
3036
#endif

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,6 @@ def simm12Plus1 : ImmLeaf<XLenVT, [{
2121
def simm12Plus1i32 : ImmLeaf<i32, [{
2222
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
2323

24-
def uimm5i32 : ImmLeaf<i32, [{return isUInt<5>(Imm);}]>;
25-
2624
// FIXME: This doesn't check that the G_CONSTANT we're deriving the immediate
2725
// from is only used once
2826
def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
@@ -87,26 +85,13 @@ def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
8785
def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
8886
def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
8987
def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
90-
91-
def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
92-
(SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
93-
def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
94-
(SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
95-
def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
96-
(SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
9788
}
9889

9990
let Predicates = [HasStdExtZba, IsRV64] in {
10091
// This pattern is put here due to the fact that i32 is not a legal type
10192
// in SDISel for RV64, which is not the case in GISel.
10293
def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
10394
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;
104-
105-
foreach i = {1,2,3} in {
106-
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
107-
def : Pat<(i32 (add_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
108-
(shxadd GPR:$rs1, GPR:$rs2)>;
109-
}
11095
} // Predicates = [HasStdExtZba, IsRV64]
11196

11297
// Ptr type used in patterns with GlobalISelEmitter

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -850,6 +850,12 @@ let Predicates = [HasStdExtZba, IsRV64] in {
850850
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
851851
def : Pat<(i64 (add_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
852852
(ADD_UW GPR:$rs1, GPR:$rs2)>;
853+
854+
foreach i = {1,2,3} in {
855+
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
856+
def : Pat<(i32 (add_non_imm12 (shl GPR:$rs1, (i64 i)), GPR:$rs2)),
857+
(shxadd GPR:$rs1, GPR:$rs2)>;
858+
}
853859
}
854860

855861
let Predicates = [HasStdExtZbs, IsRV64] in {

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -245,8 +245,8 @@ body: |
245245
; RV64I-NEXT: PseudoRET implicit $x10
246246
%0:gprb(s64) = COPY $x10
247247
%1:gprb(s32) = G_TRUNC %0(s64)
248-
%2:gprb(s32) = G_CONSTANT i32 31
249-
%3:gprb(s32) = G_SHL %1, %2(s32)
248+
%2:gprb(s64) = G_CONSTANT i64 31
249+
%3:gprb(s32) = G_SHL %1, %2(s64)
250250
%4:gprb(s64) = G_ANYEXT %3(s32)
251251
$x10 = COPY %4(s64)
252252
PseudoRET implicit $x10
@@ -297,8 +297,8 @@ body: |
297297
; RV64I-NEXT: PseudoRET implicit $x10
298298
%0:gprb(s64) = COPY $x10
299299
%1:gprb(s32) = G_TRUNC %0(s64)
300-
%2:gprb(s32) = G_CONSTANT i32 31
301-
%3:gprb(s32) = G_ASHR %1, %2(s32)
300+
%2:gprb(s64) = G_CONSTANT i64 31
301+
%3:gprb(s32) = G_ASHR %1, %2(s64)
302302
%4:gprb(s64) = G_ANYEXT %3(s32)
303303
$x10 = COPY %4(s64)
304304
PseudoRET implicit $x10
@@ -349,8 +349,8 @@ body: |
349349
; RV64I-NEXT: PseudoRET implicit $x10
350350
%0:gprb(s64) = COPY $x10
351351
%1:gprb(s32) = G_TRUNC %0(s64)
352-
%2:gprb(s32) = G_CONSTANT i32 31
353-
%3:gprb(s32) = G_LSHR %1, %2(s32)
352+
%2:gprb(s64) = G_CONSTANT i64 31
353+
%3:gprb(s32) = G_LSHR %1, %2(s64)
354354
%4:gprb(s64) = G_ANYEXT %3(s32)
355355
$x10 = COPY %4(s64)
356356
PseudoRET implicit $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ body: |
269269
%1:gprb(s64) = COPY $x11
270270
%2:gprb(s32) = G_TRUNC %0
271271
%3:gprb(s32) = G_TRUNC %1
272-
%4:gprb(s32) = G_CONSTANT i32 1
272+
%4:gprb(s64) = G_CONSTANT i64 1
273273
%5:gprb(s32) = G_SHL %2, %4
274274
%6:gprb(s32) = G_ADD %5, %3
275275
%7:gprb(s64) = G_ANYEXT %6
@@ -295,7 +295,7 @@ body: |
295295
%1:gprb(s64) = COPY $x11
296296
%2:gprb(s32) = G_TRUNC %0
297297
%3:gprb(s32) = G_TRUNC %1
298-
%4:gprb(s32) = G_CONSTANT i32 2
298+
%4:gprb(s64) = G_CONSTANT i64 2
299299
%5:gprb(s32) = G_SHL %2, %4
300300
%6:gprb(s32) = G_ADD %5, %3
301301
%7:gprb(s64) = G_ANYEXT %6
@@ -321,7 +321,7 @@ body: |
321321
%1:gprb(s64) = COPY $x11
322322
%2:gprb(s32) = G_TRUNC %0
323323
%3:gprb(s32) = G_TRUNC %1
324-
%4:gprb(s32) = G_CONSTANT i32 3
324+
%4:gprb(s64) = G_CONSTANT i64 3
325325
%5:gprb(s32) = G_SHL %2, %4
326326
%6:gprb(s32) = G_ADD %5, %3
327327
%7:gprb(s64) = G_ANYEXT %6

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-abs.mir

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,19 @@ body: |
77
; CHECK-LABEL: name: abs_i8
88
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
99
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
10-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
1110
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
12-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
13-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
14-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
15-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
11+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
12+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
13+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
14+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
15+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
16+
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C2]](s64)
1617
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64)
1718
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR1]]
1819
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
1920
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
20-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
21-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
21+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
22+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]
2223
; CHECK-NEXT: $x10 = COPY [[AND]](s64)
2324
; CHECK-NEXT: PseudoRET implicit $x10
2425
%1:_(s64) = COPY $x10
@@ -36,19 +37,20 @@ body: |
3637
; CHECK-LABEL: name: abs_i16
3738
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3839
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
39-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
4040
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
41-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
42-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32)
43-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
44-
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
41+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
42+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
43+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
44+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
45+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
46+
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C2]](s64)
4547
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
4648
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC1]], [[ASHR1]]
4749
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
4850
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
49-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
50-
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C2]](s64)
51-
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C2]](s64)
51+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
52+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C3]](s64)
53+
; CHECK-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C3]](s64)
5254
; CHECK-NEXT: $x10 = COPY [[ASHR2]](s64)
5355
; CHECK-NEXT: PseudoRET implicit $x10
5456
%1:_(s64) = COPY $x10
@@ -67,8 +69,8 @@ body: |
6769
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
6870
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
6971
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64)
70-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
71-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32)
72+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
73+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s64)
7274
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[ASHR]]
7375
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
7476
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[XOR]](s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,10 @@ body: |
1212
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
1313
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
1414
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
15-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
17-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
15+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
16+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
17+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
18+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s64)
1819
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
1920
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
2021
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -40,9 +41,10 @@ body: |
4041
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
4142
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
4243
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
43-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
44-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
45-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
44+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
45+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
46+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
47+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s64)
4648
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
4749
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
4850
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -68,9 +70,10 @@ body: |
6870
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
6971
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
7072
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
71-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
72-
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32)
73-
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
73+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
74+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s64)
75+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
76+
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s64)
7477
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
7578
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32)
7679
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)

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