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| 1 | +// RUN: %clang -std=c++11 -fsycl %s -o %t.out -lstdc++ -lOpenCL -lsycl |
| 2 | +// RUN: env SYCL_DEVICE_TYPE=HOST %t.out |
| 3 | +// RUN: %ACC_RUN_PLACEHOLDER %t.out |
| 4 | +// RUN: %CPU_RUN_PLACEHOLDER %t.out |
| 5 | +// RUN: %GPU_RUN_PLACEHOLDER %t.out |
| 6 | + |
| 7 | +#include <CL/sycl.hpp> |
| 8 | +#include <iostream> |
| 9 | + |
| 10 | +using namespace cl::sycl; |
| 11 | + |
| 12 | +const int dataSize = 32; |
| 13 | +const int maxNumQueues = 256; |
| 14 | + |
| 15 | +void GetCLQueue(event sycl_event, std::set<cl_command_queue>& cl_queues) { |
| 16 | + try { |
| 17 | + cl_command_queue cl_queue; |
| 18 | + cl_event cl_event = sycl_event.get(); |
| 19 | + cl_int error = clGetEventInfo(cl_event, CL_EVENT_COMMAND_QUEUE, |
| 20 | + sizeof(cl_queue), &cl_queue, nullptr); |
| 21 | + assert(CL_SUCCESS == error && "Failed to obtain queue from OpenCL event"); |
| 22 | + |
| 23 | + cl_queues.insert(cl_queue); |
| 24 | + } catch (invalid_object_error e) { |
| 25 | + std::cout << "Failed to get OpenCL queue from SYCL event: " << e.what() |
| 26 | + << std::endl; |
| 27 | + } |
| 28 | +} |
| 29 | + |
| 30 | +int main() { |
| 31 | + int data[dataSize] = {0}; |
| 32 | + |
| 33 | + { |
| 34 | + queue Queue; |
| 35 | + std::set<cl_command_queue> cl_queues; |
| 36 | + event sycl_event; |
| 37 | + |
| 38 | + // Purpose of this test is to check how many OpenCL queues are being |
| 39 | + // created from 1 SYCL queue for FPGA device. For that we submit 3 kernels |
| 40 | + // expecting 3 OpenCL queues created as a result. |
| 41 | + buffer<int, 1> bufA (data, range<1>(dataSize)); |
| 42 | + buffer<int, 1> bufB (data, range<1>(dataSize)); |
| 43 | + buffer<int, 1> bufC (data, range<1>(dataSize)); |
| 44 | + |
| 45 | + sycl_event = Queue.submit([&](handler& cgh) { |
| 46 | + auto writeBuffer = bufA.get_access<access::mode::write>(cgh); |
| 47 | + |
| 48 | + // Create a range. |
| 49 | + auto myRange = range<1>(dataSize); |
| 50 | + |
| 51 | + // Create a kernel. |
| 52 | + auto myKernel = ([=](id<1> idx) { |
| 53 | + writeBuffer[idx] = idx[0]; |
| 54 | + }); |
| 55 | + |
| 56 | + cgh.parallel_for<class fpga_writer_1>(myRange, myKernel); |
| 57 | + }); |
| 58 | + GetCLQueue(sycl_event, cl_queues); |
| 59 | + |
| 60 | + sycl_event = Queue.submit([&](handler& cgh) { |
| 61 | + auto writeBuffer = bufB.get_access<access::mode::write>(cgh); |
| 62 | + |
| 63 | + // Create a range. |
| 64 | + auto myRange = range<1>(dataSize); |
| 65 | + |
| 66 | + // Create a kernel. |
| 67 | + auto myKernel = ([=](id<1> idx) { |
| 68 | + writeBuffer[idx] = idx[0]; |
| 69 | + }); |
| 70 | + |
| 71 | + cgh.parallel_for<class fpga_writer_2>(myRange, myKernel); |
| 72 | + }); |
| 73 | + GetCLQueue(sycl_event, cl_queues); |
| 74 | + |
| 75 | + sycl_event = Queue.submit([&](handler& cgh) { |
| 76 | + auto readBufferA = bufA.get_access<access::mode::read>(cgh); |
| 77 | + auto readBufferB = bufB.get_access<access::mode::read>(cgh); |
| 78 | + auto writeBuffer = bufC.get_access<access::mode::write>(cgh); |
| 79 | + |
| 80 | + // Create a range. |
| 81 | + auto myRange = range<1>(dataSize); |
| 82 | + |
| 83 | + // Create a kernel. |
| 84 | + auto myKernel = ([=](id<1> idx) { |
| 85 | + writeBuffer[idx] = readBufferA[idx] + readBufferB[idx]; |
| 86 | + }); |
| 87 | + |
| 88 | + cgh.parallel_for<class fpga_calculator>(myRange, myKernel); |
| 89 | + }); |
| 90 | + GetCLQueue(sycl_event, cl_queues); |
| 91 | + |
| 92 | + int result = cl_queues.size(); |
| 93 | + device dev = Queue.get_device(); |
| 94 | + int expected_result = dev.is_accelerator() ? 3 : dev.is_host() ? 0 : 1; |
| 95 | + |
| 96 | + if (expected_result != result) { |
| 97 | + std::cout << "Result Num of queues = " << result << std::endl |
| 98 | + << "Expected Num of queues = 3" << std::endl; |
| 99 | + |
| 100 | + return -1; |
| 101 | + } |
| 102 | + |
| 103 | + auto readBufferC = bufC.get_access<access::mode::read>(); |
| 104 | + for (size_t i = 0; i != dataSize; ++i) { |
| 105 | + if (readBufferC[i] != 2 * i) { |
| 106 | + std::cout << "Result mismatches " << readBufferC[i] << " Vs expected " |
| 107 | + << 2 * i << " for index " << i << std::endl; |
| 108 | + } |
| 109 | + } |
| 110 | + } |
| 111 | + |
| 112 | + { |
| 113 | + queue Queue; |
| 114 | + std::set<cl_command_queue> cl_queues; |
| 115 | + event sycl_event; |
| 116 | + |
| 117 | + // Check limits of OpenCL queues creation for accelerator device. |
| 118 | + buffer<int, 1> buf (&data[0], range<1>(1)); |
| 119 | + |
| 120 | + for (size_t i = 0; i != maxNumQueues + 1; ++i) { |
| 121 | + sycl_event = Queue.submit([&](handler& cgh) { |
| 122 | + auto Buffer = buf.get_access<access::mode::write>(cgh); |
| 123 | + |
| 124 | + // Create a kernel. |
| 125 | + auto myKernel = ([=]() { |
| 126 | + Buffer[0] = 0; |
| 127 | + }); |
| 128 | + |
| 129 | + cgh.single_task<class fpga_kernel>(myKernel); |
| 130 | + }); |
| 131 | + GetCLQueue(sycl_event, cl_queues); |
| 132 | + } |
| 133 | + |
| 134 | + int result = cl_queues.size(); |
| 135 | + device dev = Queue.get_device(); |
| 136 | + int expected_result = dev.is_accelerator() ? maxNumQueues : |
| 137 | + dev.is_host() ? 0 : 1; |
| 138 | + |
| 139 | + if (expected_result != result) { |
| 140 | + std::cout << "Result Num of queues = " << result << std::endl |
| 141 | + << "Expected Num of queues = " << maxNumQueues << std::endl; |
| 142 | + |
| 143 | + return -1; |
| 144 | + } |
| 145 | + } |
| 146 | + |
| 147 | + return 0; |
| 148 | +} |
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