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+ ; This test demonstrates that multiple padding elements can be
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+ ; inserted in the spec constant metadata
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+
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+ ; RUN: sycl-post-link --spec-const=native -S %s -o %t.table
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+ ; RUN: FileCheck %s -input-file=%t_0.ll
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+
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+ ; CHECK: %[[#SCV1:]] = call i8 @_Z20__spirv_SpecConstantia(i32 [[#SCID1:]], i8 120)
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+ ; CHECK: %[[#SCV2:]] = call i8 @_Z20__spirv_SpecConstantia(i32 [[#SCID2:]], i8 121)
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+ ; CHECK: %[[#SCV3:]] = call i32 @_Z20__spirv_SpecConstantii(i32 [[#SCID3:]], i32 122)
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+ ; CHECK: %[[#SCV4:]] = call i8 @_Z20__spirv_SpecConstantia(i32 [[#SCID4:]], i8 97)
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+ ; CHECK: %[[#SCV5:]] = call %struct.anon @_Z29__spirv_SpecConstantCompositeaia_Rstruct.anon(i8 %[[#SCV2:]], i32 %[[#SCV3:]], i8 %[[#SCV4:]])
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+ ; CHECK: %[[#SCV6:]] = call i8 @_Z20__spirv_SpecConstantia(i32 [[#SCID5:]], i8 98)
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+ ; CHECK: call %struct.user_defined_type3 @_Z29__spirv_SpecConstantCompositeastruct.anona_Rstruct.user_defined_type3(i8 %[[#SCV1:]], %struct.anon %[[#SCV5:]], i8 %[[#SCV6:]])
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+
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+ ; CHECK: !sycl.specialization-constants = !{![[#SC:]]}
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+ ; CHECK: ![[#SC]] = !{!"uid0a28d8a0a23067ab____ZL8spec_id3",
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+ ; CHECK-SAME: i32 [[#SCID1:]], i32 0, i32 1,
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+ ; CHECK-SAME: i32 [[#SCID2:]], i32 4, i32 1,
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+ ; CHECK-SAME: i32 [[#SCID3:]], i32 8, i32 4,
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+ ; CHECK-SAME: i32 [[#SCID4:]], i32 12, i32 1,
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+ ; CHECK-SAME: i32 -1, i32 13, i32 3,
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+ ; CHECK-SAME: i32 [[#SCID5:]], i32 16, i32 1,
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+ ; CHECK-SAME: i32 -1, i32 17, i32 3}
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+
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+ ; ModuleID = '..\sycl\test-e2e\SpecConstants\2020\nested-non-packed-struct.cpp'
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+ source_filename = "..\\s ycl\\t est-e2e\\S pecConstants\\2 020\\n ested-non-packed-struct.cpp"
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+ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
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+ target triple = "spir64-unknown-unknown"
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+
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+ %"class.sycl::_V1::specialization_id.24" = type { %struct.user_defined_type3 }
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+ %struct.user_defined_type3 = type { i8 , %struct.anon , i8 }
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+ %struct.anon = type { i8 , i32 , i8 }
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+ %"class.sycl::_V1::id" = type { %"class.sycl::_V1::detail::array" }
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+ %"class.sycl::_V1::detail::array" = type { [1 x i64 ] }
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+
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+ @__usid_str.2 = private unnamed_addr constant [35 x i8 ] c "uid0a28d8a0a23067ab____ZL8spec_id3\00 " , align 1
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+ @_ZL8spec_id3 = internal addrspace (1 ) constant %"class.sycl::_V1::specialization_id.24" { %struct.user_defined_type3 { i8 120 , %struct.anon { i8 121 , i32 122 , i8 97 }, i8 98 } }, align 4
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+
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+ ; Function Attrs: convergent norecurse nounwind
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+ define weak_odr dso_local spir_kernel void @_ZTSZZ4mainENKUlRN4sycl3_V17handlerEE2_clES2_EUlNS0_14kernel_handlerEE_ (ptr addrspace (1 ) noundef align 4 %_arg_acc , ptr noundef byval (%"class.sycl::_V1::id" ) align 8 %_arg_acc3 ) local_unnamed_addr #0 !srcloc !78 !kernel_arg_buffer_location !63 !kernel_arg_runtime_aligned !64 !kernel_arg_exclusive_ptr !64 !sycl_fixed_targets !65 !sycl_kernel_omit_args !66 {
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+ entry:
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+ %ref.tmp.i = alloca %struct.user_defined_type3 , align 4
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+ %0 = load i64 , ptr %_arg_acc3 , align 8
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+ %add.ptr.i = getelementptr inbounds %struct.user_defined_type3 , ptr addrspace (1 ) %_arg_acc , i64 %0
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+ %ref.tmp.ascast.i = addrspacecast ptr %ref.tmp.i to ptr addrspace (4 )
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+ call spir_func void @_Z40__sycl_getComposite2020SpecConstantValueI18user_defined_type3ET_PKcPKvS5_ (ptr addrspace (4 ) sret (%struct.user_defined_type3 ) align 4 %ref.tmp.ascast.i , ptr addrspace (4 ) noundef addrspacecast (ptr @__usid_str.2 to ptr addrspace (4 )), ptr addrspace (4 ) noundef addrspacecast (ptr addrspace (1 ) @_ZL8spec_id3 to ptr addrspace (4 )), ptr addrspace (4 ) noundef null ) #5
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+ call void @llvm.memcpy.p1.p0.i64 (ptr addrspace (1 ) align 4 %add.ptr.i , ptr align 4 %ref.tmp.i , i64 20 , i1 false ), !tbaa.struct !79
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+ ret void
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+ }
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+
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+ ; Function Attrs: convergent nounwind
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+ declare dso_local spir_func void @_Z40__sycl_getComposite2020SpecConstantValueI18user_defined_type3ET_PKcPKvS5_ (ptr addrspace (4 ) sret (%struct.user_defined_type3 ) align 4 , ptr addrspace (4 ) noundef, ptr addrspace (4 ) noundef, ptr addrspace (4 ) noundef) local_unnamed_addr #2
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+
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+ ; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
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+ declare void @llvm.memcpy.p1.p0.i64 (ptr addrspace (1 ) noalias nocapture writeonly , ptr noalias nocapture readonly , i64 , i1 immarg) #3
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+
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+ attributes #0 = { convergent norecurse nounwind "frame-pointer" ="all" "no-trapping-math" ="true" "stack-protector-buffer-size" ="8" "sycl-module-id" ="..\\s ycl\\t est-e2e\\S pecConstants\\2 020\\n ested-non-packed-struct.cpp" "sycl-optlevel" ="2" "sycl-single-task" "uniform-work-group-size" ="true" }
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+ attributes #2 = { convergent nounwind "frame-pointer" ="all" "no-trapping-math" ="true" "stack-protector-buffer-size" ="8" }
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+ attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
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+ attributes #4 = { nounwind }
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+ attributes #5 = { convergent nounwind }
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+
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+ !llvm.dependent-libraries = !{!0 }
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+ !llvm.module.flags = !{!1 , !2 }
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+ !opencl.spir.version = !{!3 }
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+ !spirv.Source = !{!4 }
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+ !sycl_aspects = !{!5 , !6 , !7 , !8 , !9 , !10 , !11 , !12 , !13 , !14 , !15 , !16 , !17 , !18 , !19 , !20 , !21 , !22 , !23 , !24 , !25 , !26 , !27 , !28 , !29 , !30 , !31 , !32 , !33 , !34 , !35 , !36 , !37 , !38 , !39 , !40 , !41 , !42 , !43 , !44 , !45 , !46 , !47 , !48 , !49 , !50 , !51 , !52 , !53 , !54 , !55 , !56 , !57 , !58 , !59 , !60 }
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+ !llvm.ident = !{!61 }
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+
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+ !0 = !{!"libcpmt" }
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+ !1 = !{i32 1 , !"wchar_size" , i32 2 }
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+ !2 = !{i32 7 , !"frame-pointer" , i32 2 }
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+ !3 = !{i32 1 , i32 2 }
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+ !4 = !{i32 4 , i32 100000 }
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+ !5 = !{!"cpu" , i32 1 }
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+ !6 = !{!"gpu" , i32 2 }
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+ !7 = !{!"accelerator" , i32 3 }
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+ !8 = !{!"custom" , i32 4 }
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+ !9 = !{!"fp16" , i32 5 }
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+ !10 = !{!"fp64" , i32 6 }
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+ !11 = !{!"image" , i32 9 }
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+ !12 = !{!"online_compiler" , i32 10 }
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+ !13 = !{!"online_linker" , i32 11 }
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+ !14 = !{!"queue_profiling" , i32 12 }
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+ !15 = !{!"usm_device_allocations" , i32 13 }
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+ !16 = !{!"usm_host_allocations" , i32 14 }
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+ !17 = !{!"usm_shared_allocations" , i32 15 }
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+ !18 = !{!"usm_system_allocations" , i32 17 }
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+ !19 = !{!"ext_intel_pci_address" , i32 18 }
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+ !20 = !{!"ext_intel_gpu_eu_count" , i32 19 }
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+ !21 = !{!"ext_intel_gpu_eu_simd_width" , i32 20 }
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+ !22 = !{!"ext_intel_gpu_slices" , i32 21 }
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+ !23 = !{!"ext_intel_gpu_subslices_per_slice" , i32 22 }
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+ !24 = !{!"ext_intel_gpu_eu_count_per_subslice" , i32 23 }
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+ !25 = !{!"ext_intel_max_mem_bandwidth" , i32 24 }
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+ !26 = !{!"ext_intel_mem_channel" , i32 25 }
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+ !27 = !{!"usm_atomic_host_allocations" , i32 26 }
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+ !28 = !{!"usm_atomic_shared_allocations" , i32 27 }
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+ !29 = !{!"atomic64" , i32 28 }
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+ !30 = !{!"ext_intel_device_info_uuid" , i32 29 }
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+ !31 = !{!"ext_oneapi_srgb" , i32 30 }
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+ !32 = !{!"ext_oneapi_native_assert" , i32 31 }
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+ !33 = !{!"host_debuggable" , i32 32 }
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+ !34 = !{!"ext_intel_gpu_hw_threads_per_eu" , i32 33 }
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+ !35 = !{!"ext_oneapi_cuda_async_barrier" , i32 34 }
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+ !36 = !{!"ext_oneapi_bfloat16_math_functions" , i32 35 }
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+ !37 = !{!"ext_intel_free_memory" , i32 36 }
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+ !38 = !{!"ext_intel_device_id" , i32 37 }
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+ !39 = !{!"ext_intel_memory_clock_rate" , i32 38 }
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+ !40 = !{!"ext_intel_memory_bus_width" , i32 39 }
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+ !41 = !{!"emulated" , i32 40 }
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+ !42 = !{!"ext_intel_legacy_image" , i32 41 }
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+ !43 = !{!"ext_oneapi_bindless_images" , i32 42 }
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+ !44 = !{!"ext_oneapi_bindless_images_shared_usm" , i32 43 }
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+ !45 = !{!"ext_oneapi_bindless_images_1d_usm" , i32 44 }
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+ !46 = !{!"ext_oneapi_bindless_images_2d_usm" , i32 45 }
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+ !47 = !{!"ext_oneapi_interop_memory_import" , i32 46 }
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+ !48 = !{!"ext_oneapi_interop_memory_export" , i32 47 }
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+ !49 = !{!"ext_oneapi_interop_semaphore_import" , i32 48 }
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+ !50 = !{!"ext_oneapi_interop_semaphore_export" , i32 49 }
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+ !51 = !{!"ext_oneapi_mipmap" , i32 50 }
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+ !52 = !{!"ext_oneapi_mipmap_anisotropy" , i32 51 }
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+ !53 = !{!"ext_oneapi_mipmap_level_reference" , i32 52 }
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+ !54 = !{!"ext_intel_esimd" , i32 53 }
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+ !55 = !{!"ext_oneapi_non_uniform_groups" , i32 54 }
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+ !56 = !{!"int64_base_atomics" , i32 7 }
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+ !57 = !{!"int64_extended_atomics" , i32 8 }
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+ !58 = !{!"usm_system_allocator" , i32 17 }
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+ !59 = !{!"usm_restricted_shared_allocations" , i32 16 }
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+ !60 = !{!"host" , i32 0 }
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+ !61 = !{!"clang version 18.0.0 (https://github.com/intel/llvm.git c92b6b0c266b6a0d5bca1d61a63f06e2bce37904)" }
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+ !62 = !{i32 2091 }
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+ !63 = !{i32 -1 , i32 -1 }
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+ !64 = !{i1 true , i1 false }
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+ !65 = !{}
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+ !66 = !{i1 false , i1 true , i1 true , i1 false , i1 true }
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+ !67 = !{i64 0 , i64 4 , !68 , i64 4 , i64 1 , !72 , i64 8 , i64 4 , !73 }
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+ !68 = !{!69 , !69 , i64 0 }
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+ !69 = !{!"float" , !70 , i64 0 }
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+ !70 = !{!"omnipotent char" , !71 , i64 0 }
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+ !71 = !{!"Simple C++ TBAA" }
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+ !72 = !{!70 , !70 , i64 0 }
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+ !73 = !{!74 , !74 , i64 0 }
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+ !74 = !{!"int" , !70 , i64 0 }
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+ !75 = !{i32 2451 }
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+ !76 = !{i64 0 , i64 4 , !68 , i64 32 , i64 4 , !68 , i64 36 , i64 1 , !72 , i64 40 , i64 4 , !73 , i64 64 , i64 4 , !73 , i64 68 , i64 1 , !72 }
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+ !77 = !{i32 2882 }
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+ !78 = !{i32 3230 }
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+ !79 = !{i64 0 , i64 1 , !72 , i64 4 , i64 1 , !72 , i64 8 , i64 4 , !73 , i64 12 , i64 1 , !72 , i64 16 , i64 1 , !72 }
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