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Allow Intel Loop Controls only with SPV_INTEL_fpga_loop_controls
Added the appropriate checks if the extension is allowed. Signed-off-by: Dmitry Sidorov <[email protected]>
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6 files changed

+84
-30
lines changed

6 files changed

+84
-30
lines changed

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 34 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -779,9 +779,9 @@ class LLVMParallelAccessIndices {
779779
/// Go through the operands !llvm.loop metadata attached to the branch
780780
/// instruction, fill the Loop Control mask and possible parameters for its
781781
/// fields.
782-
static spv::LoopControlMask
783-
getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
784-
LLVMToSPIRV::LLVMToSPIRVMetadataMap &IndexGroupArrayMap) {
782+
spv::LoopControlMask
783+
LLVMToSPIRV::getLoopControl(const BranchInst *Branch,
784+
std::vector<SPIRVWord> &Parameters) {
785785
if (!Branch)
786786
return spv::LoopControlMaskNone;
787787
MDNode *LoopMD = Branch->getMetadata("llvm.loop");
@@ -821,26 +821,34 @@ getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
821821
size_t I = getMDOperandAsInt(Node, 1);
822822
Parameters.push_back(I);
823823
LoopControl |= spv::LoopControlDependencyLengthMask;
824-
} else if (S == "llvm.loop.ii.count") {
825-
size_t I = getMDOperandAsInt(Node, 1);
826-
Parameters.push_back(I);
827-
LoopControl |= spv::LoopControlInitiationIntervalINTEL;
828-
} else if (S == "llvm.loop.max_concurrency.count") {
829-
size_t I = getMDOperandAsInt(Node, 1);
830-
Parameters.push_back(I);
831-
LoopControl |= spv::LoopControlMaxConcurrencyINTEL;
832-
} else if (S == "llvm.loop.parallel_access_indices") {
833-
// Intel FPGA IVDep loop attribute
834-
LLVMParallelAccessIndices IVDep(Node, IndexGroupArrayMap);
835-
IVDep.initialize();
836-
// Store IVDep-specific parameters into an intermediate
837-
// container to address the case when there're multiple
838-
// IVDep metadata nodes and this condition gets entered multiple
839-
// times. The update of the main parameters vector & the loop control
840-
// mask will be done later, in the main scope of the function
841-
unsigned SafeLen = IVDep.getSafeLen();
842-
for (auto &ArrayId : IVDep.getArrayVariables())
843-
DependencyArrayParameters.emplace_back(ArrayId, SafeLen);
824+
} else if (BM->isAllowedToUseExtension(
825+
ExtensionID::SPV_INTEL_fpga_loop_controls)) {
826+
// Add Intel specific Loop Control masks
827+
if (S == "llvm.loop.ii.count") {
828+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
829+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
830+
size_t I = getMDOperandAsInt(Node, 1);
831+
Parameters.push_back(I);
832+
LoopControl |= spv::LoopControlInitiationIntervalINTEL;
833+
} else if (S == "llvm.loop.max_concurrency.count") {
834+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
835+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
836+
size_t I = getMDOperandAsInt(Node, 1);
837+
Parameters.push_back(I);
838+
LoopControl |= spv::LoopControlMaxConcurrencyINTEL;
839+
} else if (S == "llvm.loop.parallel_access_indices") {
840+
// Intel FPGA IVDep loop attribute
841+
LLVMParallelAccessIndices IVDep(Node, IndexGroupArrayMap);
842+
IVDep.initialize();
843+
// Store IVDep-specific parameters into an intermediate
844+
// container to address the case when there're multiple
845+
// IVDep metadata nodes and this condition gets entered multiple
846+
// times. The update of the main parameters vector & the loop control
847+
// mask will be done later, in the main scope of the function
848+
unsigned SafeLen = IVDep.getSafeLen();
849+
for (auto &ArrayId : IVDep.getArrayVariables())
850+
DependencyArrayParameters.emplace_back(ArrayId, SafeLen);
851+
}
844852
}
845853
}
846854
}
@@ -855,6 +863,8 @@ getLoopControl(const BranchInst *Branch, std::vector<SPIRVWord> &Parameters,
855863
Parameters.push_back(ArraySflnPair.first);
856864
Parameters.push_back(ArraySflnPair.second);
857865
}
866+
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
867+
BM->addCapability(CapabilityFPGALoopControlsINTEL);
858868
LoopControl |= spv::LoopControlDependencyArrayINTEL;
859869
}
860870

@@ -1066,8 +1076,7 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V,
10661076
/// with true edge going to the header and the false edge going out of
10671077
/// the loop, which corresponds to a "Merge Block" per the SPIR-V spec.
10681078
std::vector<SPIRVWord> Parameters;
1069-
spv::LoopControlMask LoopControl =
1070-
getLoopControl(Branch, Parameters, IndexGroupArrayMap);
1079+
spv::LoopControlMask LoopControl = getLoopControl(Branch, Parameters);
10711080

10721081
if (Branch->isUnconditional()) {
10731082
// For "for" and "while" loops llvm.loop metadata is attached to

‎llvm-spirv/lib/SPIRV/SPIRVWriter.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,9 @@ class LLVMToSPIRV : public ModulePass {
8585

8686
SPIRVValue *getTranslatedValue(const Value *) const;
8787

88+
spv::LoopControlMask getLoopControl(const BranchInst *Branch,
89+
std::vector<SPIRVWord> &Parameters);
90+
8891
// Translation functions
8992
bool transAddressingMode();
9093
bool transAlign(Value *V, SPIRVValue *BV);

‎llvm-spirv/test/transcoding/FPGAIVDepLoopAttr.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@
5252
; }
5353

5454
; RUN: llvm-as < %s > %t.bc
55-
; RUN: llvm-spirv %t.bc -o %t.spv
55+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_loop_controls -o %t.spv
5656
; RUN: llvm-spirv -to-text %t.spv -o %t.spt
5757
; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
5858

@@ -72,6 +72,9 @@ target triple = "spir64-unknown-unknown-sycldevice"
7272

7373
%"class._ZTSZ4mainE3$_0.anon" = type { i8 }
7474

75+
; CHECK-SPIRV: 2 Capability FPGALoopControlsINTEL
76+
; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_loop_controls"
77+
7578
; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT_64:[0-9]+]] 64 0
7679
; CHECK-SPIRV-DAG: TypeInt [[TYPE_INT_32:[0-9]+]] 32 0
7780
; CHECK-SPIRV-DAG: Constant [[TYPE_INT_64]] [[SIZE:[0-9]+]] 10 0

‎llvm-spirv/test/transcoding/FPGALoopAttr.ll

Lines changed: 36 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,21 @@
11
; RUN: llvm-as < %s > %t.bc
2-
; RUN: llvm-spirv %t.bc -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPIRV
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_loop_controls -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPIRV
33

4-
; RUN: llvm-spirv %t.bc -o %t.spv
4+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_loop_controls -o %t.spv
55
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
66
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
77

8+
; RUN: llvm-spirv %t.bc -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPIRV-NEGATIVE
9+
10+
; RUN: llvm-spirv %t.bc -o %t.spv
11+
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
12+
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM-NEGATIVE
13+
14+
; CHECK-SPIRV: 2 Capability FPGALoopControlsINTEL
15+
; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_loop_controls"
16+
; CHECK-SPIRV-NEGATIVE-NOT: 2 Capability FPGALoopControlsINTEL
17+
; CHECK-SPIRV-NEGATIVE-NOT: 9 Extension "SPV_INTEL_fpga_loop_controls"
18+
819
; ModuleID = 'FPGALoopAttr.cl'
920
source_filename = "FPGALoopAttr.cl"
1021
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
@@ -25,6 +36,8 @@ entry:
2536
; Per SPIR-V spec, LoopControlDependencyInfiniteMask = 0x00000004
2637
; CHECK-SPIRV: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 4
2738
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
39+
; CHECK-SPIRV-NEGATIVE: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 4
40+
; CHECK-SPIRV-NEGATIVE-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
2841
for.cond: ; preds = %for.inc, %entry
2942
%0 = load i32, i32* %i, align 4
3043
%cmp = icmp ne i32 %0, 10
@@ -50,6 +63,8 @@ for.end: ; preds = %for.cond
5063
; Per SPIR-V spec, LoopControlDependencyLengthMask = 0x00000008
5164
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 8 2
5265
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
66+
; CHECK-SPIRV-NEGATIVE: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 8 2
67+
; CHECK-SPIRV-NEGATIVE-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
5368
for.cond2: ; preds = %for.inc7, %for.end
5469
%3 = load i32, i32* %i1, align 4
5570
%cmp3 = icmp ne i32 %3, 10
@@ -76,6 +91,7 @@ for.end9: ; preds = %for.cond2
7691
; LoopControlInitiationIntervalINTEL = 0x10000 (65536)
7792
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 65536 2
7893
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
94+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 65536 2
7995
for.cond11: ; preds = %for.inc16, %for.end9
8096
%6 = load i32, i32* %i10, align 4
8197
%cmp12 = icmp ne i32 %6, 10
@@ -102,6 +118,7 @@ for.end18: ; preds = %for.cond11
102118
; LoopControlMaxConcurrencyINTEL = 0x20000 (131072)
103119
; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 131072 2
104120
; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
121+
; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 131072 2
105122
for.cond20: ; preds = %for.inc25, %for.end18
106123
%9 = load i32, i32* %i19, align 4
107124
%cmp21 = icmp ne i32 %9, 10
@@ -128,6 +145,7 @@ for.end27: ; preds = %for.cond20
128145
; LoopControlInitiationIntervalINTEL & LoopControlMaxConcurrencyINTEL = 0x10000 & 0x20000 = 0x30000 (196608)
129146
; CHECK-SPIRV: 6 LoopMerge {{[0-9]+}} {{[0-9]+}} 196608 2 2
130147
; CHECK-SPIRV: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
148+
; CHECK-SPIRV-NEGATIVE-NOT: 6 LoopMerge {{[0-9]+}} {{[0-9]+}} 196608 2 2
131149
for.cond29: ; preds = %for.inc34, %for.end27
132150
%12 = load i32, i32* %i28, align 4
133151
%cmp30 = icmp ne i32 %12, 10
@@ -175,6 +193,12 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
175193
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_D:[0-9]+]]
176194
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_E:[0-9]+]]
177195

196+
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_A:[0-9]+]]
197+
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]]
198+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_C:[0-9]+]]
199+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_D:[0-9]+]]
200+
; CHECK-LLVM-NEGATIVE-NOT: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_E:[0-9]+]]
201+
178202
; CHECK-LLVM: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]}
179203
; CHECK-LLVM: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"}
180204
; CHECK-LLVM: ![[MD_B]] = distinct !{![[MD_B]], ![[MD_ivdep:[0-9]+]]}
@@ -184,3 +208,13 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
184208
; CHECK-LLVM: ![[MD_D]] = distinct !{![[MD_D]], ![[MD_max_concurrency:[0-9]+]]}
185209
; CHECK-LLVM: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 2}
186210
; CHECK-LLVM: ![[MD_E]] = distinct !{![[MD_E]], ![[MD_ii:[0-9]+]], ![[MD_max_concurrency:[0-9]+]]}
211+
212+
; CHECK-LLVM-NEGATIVE: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]}
213+
; CHECK-LLVM-NEGATIVE: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"}
214+
; CHECK-LLVM-NEGATIVE: ![[MD_B]] = distinct !{![[MD_B]], ![[MD_ivdep:[0-9]+]]}
215+
; CHECK-LLVM-NEGATIVE: ![[MD_ivdep]] = !{!"llvm.loop.ivdep.safelen", i32 2}
216+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_C]] = distinct !{![[MD_C]], ![[MD_ii:[0-9]+]]}
217+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_ii]] = !{!"llvm.loop.ii.count", i32 2}
218+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_D]] = distinct !{![[MD_D]], ![[MD_max_concurrency:[0-9]+]]}
219+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 2}
220+
; CHECK-LLVM-NEGATIVE-NOT: ![[MD_E]] = distinct !{![[MD_E]], ![[MD_ii:[0-9]+]], ![[MD_max_concurrency:[0-9]+]]}

‎llvm-spirv/test/transcoding/FPGALoopMergeInst.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,9 @@
5959
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
6060
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
6161

62+
; CHECK-SPIRV: 2 Capability FPGALoopControlsINTEL
63+
; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_loop_controls"
64+
6265
; CHECK-SPIRV: 6 Name [[FOR:[0-9]+]] "while.body20"
6366

6467
; ModuleID = 'FPGALoopMergeInst.cpp'

‎llvm-spirv/test/transcoding/FPGAUnstructuredLoopAttr.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,13 @@
11
; RUN: llvm-as < %s > %t.bc
2-
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_unstructured_loop_controls -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPIRV
2+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_unstructured_loop_controls --spirv-ext=+SPV_INTEL_fpga_loop_controls -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPIRV
33

4-
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_unstructured_loop_controls -o %t.spv
4+
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_unstructured_loop_controls --spirv-ext=+SPV_INTEL_fpga_loop_controls -o %t.spv
55
; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
66
; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
77

88
; CHECK-SPIRV: 2 Capability UnstructuredLoopControlsINTEL
9+
; CHECK-SPIRV: 2 Capability FPGALoopControlsINTEL
10+
; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_loop_controls"
911
; CHECK-SPIRV: 11 Extension "SPV_INTEL_unstructured_loop_controls"
1012
; CHECK-SPIRV: 4 EntryPoint 6 [[FOO:[0-9]+]] "foo"
1113
; CHECK-SPIRV: 4 EntryPoint 6 [[BOO:[0-9]+]] "boo"

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