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[SYCL] Add an attr tablegen feature for checking langopts (#3234)
For SYCL, we want some attributes to be ignored in host mode, but without diagnosing the attribute as being ignored. This adds a bit to the tablegen emitter to specify that a given language option opts into this behavior. This allows us to more naturally specify that an attribute is a device-only attribute from Attr.td without adding logic in SemaDeclAttr.cpp to bail out in host mode (which looks like a bug due to the lack of an ignored attribute warning). As a drive-by, this also corrects a think-o with the [[intel::reqd_sub_group_size]] attribute in OpenCL mode, which was always being silently dropped.
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+42
-76
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4 files changed

+42
-76
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clang/include/clang/Basic/Attr.td

Lines changed: 28 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -317,10 +317,14 @@ class SubjectList<list<AttrSubject> subjects, SubjectDiag diag = WarnDiag,
317317
string CustomDiag = customDiag;
318318
}
319319

320-
class LangOpt<string name, code customCode = [{}]> {
320+
class LangOpt<string name, code customCode = [{}], bit silentlyIgnore = 0> {
321321
// The language option to test; ignored when custom code is supplied.
322322
string Name = name;
323323

324+
// If set to 1, the attribute is accepted but is silently ignored. This is
325+
// useful in multi-compilation situations like SYCL.
326+
bit SilentlyIgnore = silentlyIgnore;
327+
324328
// A custom predicate, written as an expression evaluated in a context with
325329
// "LangOpts" bound.
326330
code CustomCode = customCode;
@@ -329,9 +333,10 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">;
329333
def Borland : LangOpt<"Borland">;
330334
def CUDA : LangOpt<"CUDA">;
331335
def HIP : LangOpt<"HIP">;
336+
def SYCL : LangOpt<"SYCL">;
332337
def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
333-
def SYCL : LangOpt<"SYCLIsDevice">;
334338
def SYCLIsHost : LangOpt<"SYCLIsHost">;
339+
def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 1>;
335340
def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
336341
def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
337342
def CPlusPlus : LangOpt<"CPlusPlus">;
@@ -1322,7 +1327,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
13221327
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
13231328
CXX11<"intel","no_global_work_offset">];
13241329
let Args = [ExprArgument<"Value", /*optional*/1>];
1325-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1330+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13261331
let Subjects = SubjectList<[Function], ErrorDiag>;
13271332
let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
13281333
}
@@ -1331,7 +1336,7 @@ def SYCLIntelLoopFuse : InheritableAttr {
13311336
let Spellings = [CXX11<"intel", "loop_fuse">,
13321337
CXX11<"intel", "loop_fuse_independent">];
13331338
let Args = [ExprArgument<"Value", /*optional=*/ 1>];
1334-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1339+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13351340
let Subjects = SubjectList<[Function], ErrorDiag>;
13361341
let Accessors = [Accessor<"isIndependent",
13371342
[CXX11<"intel", "loop_fuse_independent">]>];
@@ -1395,7 +1400,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
13951400
let Args = [ExprArgument<"Value">];
13961401
let Subjects = SubjectList<[Function], ErrorDiag>;
13971402
let Documentation = [IntelReqdSubGroupSizeDocs];
1398-
let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
1403+
let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
13991404
}
14001405

14011406
// This attribute is both a type attribute, and a declaration attribute (for
@@ -1841,7 +1846,7 @@ def SYCLIntelFPGAInitiationInterval : StmtAttr {
18411846
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18421847
ErrorDiag, "'for', 'while', and 'do' statements">;
18431848
let Args = [ExprArgument<"IntervalExpr">];
1844-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1849+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18451850
let HasCustomTypeTransform = 1;
18461851
let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs];
18471852
}
@@ -1852,7 +1857,7 @@ def SYCLIntelFPGAMaxConcurrency : StmtAttr {
18521857
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18531858
ErrorDiag, "'for', 'while', and 'do' statements">;
18541859
let Args = [ExprArgument<"NThreadsExpr">];
1855-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1860+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18561861
let HasCustomTypeTransform = 1;
18571862
let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
18581863
}
@@ -1863,7 +1868,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
18631868
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18641869
ErrorDiag, "'for', 'while', and 'do' statements">;
18651870
let Args = [ExprArgument<"NExpr">];
1866-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1871+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18671872
let HasCustomTypeTransform = 1;
18681873
let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
18691874
}
@@ -1873,7 +1878,7 @@ def SYCLIntelFPGADisableLoopPipelining : StmtAttr {
18731878
CXX11<"intel","disable_loop_pipelining">];
18741879
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18751880
ErrorDiag, "'for', 'while', and 'do' statements">;
1876-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1881+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18771882
let HasCustomTypeTransform = 1;
18781883
let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
18791884
}
@@ -1884,7 +1889,7 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
18841889
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18851890
ErrorDiag, "'for', 'while', and 'do' statements">;
18861891
let Args = [ExprArgument<"NExpr">];
1887-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1892+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18881893
let HasCustomTypeTransform = 1;
18891894
let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
18901895
}
@@ -1895,7 +1900,7 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
18951900
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
18961901
ErrorDiag, "'for', 'while', and 'do' statements">;
18971902
let Args = [ExprArgument<"NExpr">];
1898-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1903+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
18991904
let HasCustomTypeTransform = 1;
19001905
let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
19011906
}
@@ -1904,7 +1909,7 @@ def SYCLIntelFPGANofusion : StmtAttr {
19041909
let Spellings = [CXX11<"intel","nofusion">];
19051910
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
19061911
ErrorDiag, "'for', 'while', and 'do' statements">;
1907-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1912+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19081913
let HasCustomTypeTransform = 1;
19091914
let Documentation = [SYCLIntelFPGANofusionAttrDocs];
19101915
}
@@ -1946,7 +1951,7 @@ def IntelFPGADoublePump : Attr {
19461951
CXX11<"intel", "doublepump">];
19471952
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19481953
Field], ErrorDiag>;
1949-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1954+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19501955
let Documentation = [IntelFPGADoublePumpAttrDocs];
19511956
}
19521957

@@ -1955,7 +1960,7 @@ def IntelFPGASinglePump : Attr {
19551960
CXX11<"intel", "singlepump">];
19561961
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19571962
Field], ErrorDiag>;
1958-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1963+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19591964
let Documentation = [IntelFPGASinglePumpAttrDocs];
19601965
}
19611966

@@ -1976,7 +1981,7 @@ def IntelFPGAMemory : Attr {
19761981
}];
19771982
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19781983
Field], ErrorDiag>;
1979-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1984+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19801985
let Documentation = [IntelFPGAMemoryAttrDocs];
19811986
}
19821987

@@ -1985,7 +1990,7 @@ def IntelFPGARegister : Attr {
19851990
CXX11<"intel", "fpga_register">];
19861991
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19871992
Field], ErrorDiag>;
1988-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
1993+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
19891994
let Documentation = [IntelFPGARegisterAttrDocs];
19901995
}
19911996

@@ -1996,7 +2001,7 @@ def IntelFPGABankWidth : Attr {
19962001
let Args = [ExprArgument<"Value">];
19972002
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19982003
Field], ErrorDiag>;
1999-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2004+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20002005
let Documentation = [IntelFPGABankWidthAttrDocs];
20012006
}
20022007

@@ -2006,15 +2011,15 @@ def IntelFPGANumBanks : Attr {
20062011
let Args = [ExprArgument<"Value">];
20072012
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20082013
Field], ErrorDiag>;
2009-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2014+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20102015
let Documentation = [IntelFPGANumBanksAttrDocs];
20112016
}
20122017

20132018
def IntelFPGAPrivateCopies : InheritableAttr {
20142019
let Spellings = [CXX11<"intelfpga","private_copies">,
20152020
CXX11<"intel","private_copies">];
20162021
let Args = [ExprArgument<"Value">];
2017-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2022+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20182023
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
20192024
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
20202025
}
@@ -2026,7 +2031,7 @@ def IntelFPGAMerge : Attr {
20262031
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
20272032
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
20282033
Field], ErrorDiag>;
2029-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2034+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20302035
let Documentation = [IntelFPGAMergeAttrDocs];
20312036
}
20322037

@@ -2036,7 +2041,7 @@ def IntelFPGAMaxReplicates : Attr {
20362041
let Args = [ExprArgument<"Value">];
20372042
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20382043
Field], ErrorDiag>;
2039-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2044+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20402045
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
20412046
}
20422047

@@ -2045,7 +2050,7 @@ def IntelFPGASimpleDualPort : Attr {
20452050
CXX11<"intel","simple_dual_port">];
20462051
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20472052
Field], ErrorDiag>;
2048-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2053+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20492054
let Documentation = [IntelFPGASimpleDualPortAttrDocs];
20502055
}
20512056

@@ -2081,7 +2086,7 @@ def IntelFPGAForcePow2Depth : Attr {
20812086
let Args = [ExprArgument<"Value">];
20822087
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20832088
Field], ErrorDiag>;
2084-
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2089+
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
20852090
let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
20862091
let AdditionalMembers = [{
20872092
static unsigned getMinValue() {

clang/lib/Sema/SemaDeclAttr.cpp

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -3211,9 +3211,6 @@ static void handleWorkGroupSizeHint(Sema &S, Decl *D, const ParsedAttr &AL) {
32113211

32123212
void Sema::AddIntelReqdSubGroupSize(Decl *D, const AttributeCommonInfo &CI,
32133213
Expr *E) {
3214-
if (LangOpts.SYCLIsHost)
3215-
return;
3216-
32173214
if (!E->isValueDependent()) {
32183215
// Validate that we have an integer constant expression and then store the
32193216
// converted constant expression into the semantic attribute so that we
@@ -3470,10 +3467,6 @@ void Sema::addSYCLIntelLoopFuseAttr(Decl *D, const AttributeCommonInfo &CI,
34703467
if (checkSYCLIntelLoopFuseArgument(*this, CI, E))
34713468
return;
34723469

3473-
// Attribute should not be added during host compilation.
3474-
if (getLangOpts().SYCLIsHost)
3475-
return;
3476-
34773470
SYCLIntelLoopFuseAttr *NewAttr = mergeSYCLIntelLoopFuseAttr(D, CI, E);
34783471

34793472
if (NewAttr)
@@ -5717,9 +5710,6 @@ static bool checkForDuplicateAttribute(Sema &S, Decl *D,
57175710

57185711
static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
57195712
const ParsedAttr &A) {
5720-
if (S.LangOpts.SYCLIsHost)
5721-
return;
5722-
57235713
checkForDuplicateAttribute<SYCLIntelNoGlobalWorkOffsetAttr>(S, D, A);
57245714
S.CheckDeprecatedSYCLAttributeSpelling(A);
57255715

@@ -5736,9 +5726,6 @@ static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
57365726
/// Both are incompatible with the __register__ attribute.
57375727
template <typename AttrType, typename IncompatAttrType>
57385728
static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) {
5739-
if (S.LangOpts.SYCLIsHost)
5740-
return;
5741-
57425729
checkForDuplicateAttribute<AttrType>(S, D, A);
57435730
if (checkAttrMutualExclusion<IncompatAttrType>(S, D, A))
57445731
return;
@@ -5759,10 +5746,6 @@ static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) {
57595746
/// This is incompatible with the [[intelfpga::register]] attribute.
57605747
static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D,
57615748
const ParsedAttr &AL) {
5762-
5763-
if (S.LangOpts.SYCLIsHost)
5764-
return;
5765-
57665749
checkForDuplicateAttribute<IntelFPGAMemoryAttr>(S, D, AL);
57675750
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
57685751
return;
@@ -5832,10 +5815,6 @@ static bool checkIntelFPGARegisterAttrCompatibility(Sema &S, Decl *D,
58325815
/// Handle the [[intelfpga::register]] attribute.
58335816
/// This is incompatible with most of the other memory attributes.
58345817
static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {
5835-
5836-
if (S.LangOpts.SYCLIsHost)
5837-
return;
5838-
58395818
checkForDuplicateAttribute<IntelFPGARegisterAttr>(S, D, A);
58405819
if (checkIntelFPGARegisterAttrCompatibility(S, D, A))
58415820
return;
@@ -5853,10 +5832,6 @@ static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {
58535832
template <typename AttrType>
58545833
static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D,
58555834
const ParsedAttr &A) {
5856-
5857-
if (S.LangOpts.SYCLIsHost)
5858-
return;
5859-
58605835
checkForDuplicateAttribute<AttrType>(S, D, A);
58615836
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
58625837
return;
@@ -5868,9 +5843,6 @@ static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D,
58685843

58695844
static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D,
58705845
const ParsedAttr &AL) {
5871-
if (S.LangOpts.SYCLIsHost)
5872-
return;
5873-
58745846
checkForDuplicateAttribute<IntelFPGASimpleDualPortAttr>(S, D, AL);
58755847

58765848
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
@@ -5888,9 +5860,6 @@ static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D,
58885860

58895861
static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
58905862
const ParsedAttr &A) {
5891-
if (S.LangOpts.SYCLIsHost)
5892-
return;
5893-
58945863
checkForDuplicateAttribute<IntelFPGAMaxReplicatesAttr>(S, D, A);
58955864

58965865
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
@@ -5908,9 +5877,6 @@ static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
59085877
static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
59095878
checkForDuplicateAttribute<IntelFPGAMergeAttr>(S, D, AL);
59105879

5911-
if (S.LangOpts.SYCLIsHost)
5912-
return;
5913-
59145880
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
59155881
return;
59165882

@@ -6029,9 +5995,6 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
60295995

60305996
static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,
60315997
const ParsedAttr &A) {
6032-
if (S.LangOpts.SYCLIsHost)
6033-
return;
6034-
60355998
checkForDuplicateAttribute<IntelFPGAPrivateCopiesAttr>(S, D, A);
60365999
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))
60376000
return;
@@ -6043,9 +6006,6 @@ static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,
60436006

60446007
static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D,
60456008
const ParsedAttr &A) {
6046-
if (S.LangOpts.SYCLIsHost)
6047-
return;
6048-
60496009
checkForDuplicateAttribute<IntelFPGAForcePow2DepthAttr>(S, D, A);
60506010

60516011
if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, A))

clang/test/CodeGenSYCL/loop_fusion_host.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s
2-
// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -verify -Wno-sycl-2017-compat -DDIAG %s
32

43
template <typename name, typename Func>
54
__attribute__((sycl_kernel)) void kernel(const Func &kernelFunc) {
@@ -30,8 +29,3 @@ void foo() {
3029
kernel<class kernel_name_1>(f5);
3130
}
3231
// CHECK-NOT: !loop_fuse
33-
34-
#if defined(DIAG)
35-
int baz();
36-
[[intel::loop_fuse(baz())]] void func3(); // expected-error{{'loop_fuse' attribute requires an integer constant}}
37-
#endif

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