@@ -317,10 +317,14 @@ class SubjectList<list<AttrSubject> subjects, SubjectDiag diag = WarnDiag,
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string CustomDiag = customDiag;
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}
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- class LangOpt<string name, code customCode = [{}]> {
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+ class LangOpt<string name, code customCode = [{}], bit silentlyIgnore = 0 > {
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// The language option to test; ignored when custom code is supplied.
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string Name = name;
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+ // If set to 1, the attribute is accepted but is silently ignored. This is
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+ // useful in multi-compilation situations like SYCL.
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+ bit SilentlyIgnore = silentlyIgnore;
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+
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// A custom predicate, written as an expression evaluated in a context with
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// "LangOpts" bound.
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code CustomCode = customCode;
@@ -329,9 +333,10 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">;
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def Borland : LangOpt<"Borland">;
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def CUDA : LangOpt<"CUDA">;
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def HIP : LangOpt<"HIP">;
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+ def SYCL : LangOpt<"SYCL">;
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def SYCLIsDevice : LangOpt<"SYCLIsDevice">;
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- def SYCL : LangOpt<"SYCLIsDevice">;
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def SYCLIsHost : LangOpt<"SYCLIsHost">;
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+ def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 1>;
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def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">;
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def COnly : LangOpt<"", "!LangOpts.CPlusPlus">;
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def CPlusPlus : LangOpt<"CPlusPlus">;
@@ -1322,7 +1327,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
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CXX11<"intel","no_global_work_offset">];
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let Args = [ExprArgument<"Value", /*optional*/1>];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
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}
@@ -1331,7 +1336,7 @@ def SYCLIntelLoopFuse : InheritableAttr {
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let Spellings = [CXX11<"intel", "loop_fuse">,
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CXX11<"intel", "loop_fuse_independent">];
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let Args = [ExprArgument<"Value", /*optional=*/ 1>];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Accessors = [Accessor<"isIndependent",
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[CXX11<"intel", "loop_fuse_independent">]>];
@@ -1395,7 +1400,7 @@ def IntelReqdSubGroupSize: InheritableAttr {
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let Args = [ExprArgument<"Value">];
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let Subjects = SubjectList<[Function], ErrorDiag>;
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let Documentation = [IntelReqdSubGroupSizeDocs];
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- let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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}
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// This attribute is both a type attribute, and a declaration attribute (for
@@ -1841,7 +1846,7 @@ def SYCLIntelFPGAInitiationInterval : StmtAttr {
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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let Args = [ExprArgument<"IntervalExpr">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs];
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}
@@ -1852,7 +1857,7 @@ def SYCLIntelFPGAMaxConcurrency : StmtAttr {
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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let Args = [ExprArgument<"NThreadsExpr">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
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}
@@ -1863,7 +1868,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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let Args = [ExprArgument<"NExpr">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
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}
@@ -1873,7 +1878,7 @@ def SYCLIntelFPGADisableLoopPipelining : StmtAttr {
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CXX11<"intel","disable_loop_pipelining">];
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
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}
@@ -1884,7 +1889,7 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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let Args = [ExprArgument<"NExpr">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
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}
@@ -1895,7 +1900,7 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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let Args = [ExprArgument<"NExpr">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
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}
@@ -1904,7 +1909,7 @@ def SYCLIntelFPGANofusion : StmtAttr {
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let Spellings = [CXX11<"intel","nofusion">];
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let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
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ErrorDiag, "'for', 'while', and 'do' statements">;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let HasCustomTypeTransform = 1;
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let Documentation = [SYCLIntelFPGANofusionAttrDocs];
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}
@@ -1946,7 +1951,7 @@ def IntelFPGADoublePump : Attr {
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CXX11<"intel", "doublepump">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGADoublePumpAttrDocs];
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}
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@@ -1955,7 +1960,7 @@ def IntelFPGASinglePump : Attr {
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CXX11<"intel", "singlepump">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGASinglePumpAttrDocs];
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}
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@@ -1976,7 +1981,7 @@ def IntelFPGAMemory : Attr {
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}];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGAMemoryAttrDocs];
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}
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@@ -1985,7 +1990,7 @@ def IntelFPGARegister : Attr {
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CXX11<"intel", "fpga_register">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGARegisterAttrDocs];
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}
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@@ -1996,7 +2001,7 @@ def IntelFPGABankWidth : Attr {
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let Args = [ExprArgument<"Value">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGABankWidthAttrDocs];
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}
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@@ -2006,15 +2011,15 @@ def IntelFPGANumBanks : Attr {
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let Args = [ExprArgument<"Value">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGANumBanksAttrDocs];
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}
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def IntelFPGAPrivateCopies : InheritableAttr {
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let Spellings = [CXX11<"intelfpga","private_copies">,
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CXX11<"intel","private_copies">];
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let Args = [ExprArgument<"Value">];
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
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let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
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}
@@ -2026,7 +2031,7 @@ def IntelFPGAMerge : Attr {
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let Args = [StringArgument<"Name">, StringArgument<"Direction">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGAMergeAttrDocs];
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}
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@@ -2036,7 +2041,7 @@ def IntelFPGAMaxReplicates : Attr {
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let Args = [ExprArgument<"Value">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
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}
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@@ -2045,7 +2050,7 @@ def IntelFPGASimpleDualPort : Attr {
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CXX11<"intel","simple_dual_port">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGASimpleDualPortAttrDocs];
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}
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@@ -2081,7 +2086,7 @@ def IntelFPGAForcePow2Depth : Attr {
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let Args = [ExprArgument<"Value">];
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let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
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Field], ErrorDiag>;
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- let LangOpts = [SYCLIsDevice, SYCLIsHost ];
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+ let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost ];
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let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
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let AdditionalMembers = [{
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static unsigned getMinValue() {
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