[CI][Container] Create new container that combines build and intel driver containers (#15668)

This container is a version of the intel_drivers container that is built
on top of our build container, instead of base. This container is needed
to be able to build all e2e tests.

---------

Co-authored-by: david.garcia.orozco <[email protected]>

Author: ayylol

.github/workflows/sycl-containers.yaml

@@ -51,6 +51,13 @@ jobs:
             file: ubuntu2204_intel_drivers
             tag: unstable
             build_args: "use_latest=true"
+          - name: Build + Intel Drivers Ubuntu 22.04 Docker image
+            file: ubuntu2204_intel_drivers
+            tag: alldeps
+            build_args: |
+              base_image=ghcr.io/intel/llvm/ubuntu2204_build
+              base_tag=latest
+              use_latest=false
     steps:
       - name: Checkout
         uses: actions/checkout@v4

sycl/doc/developer/DockerBKMs.md

@@ -40,14 +40,16 @@ The following containers are publicly available for DPC++ compiler development:
    building DPC++ compiler from source.
 - `ghcr.io/intel/llvm/ubuntu2204_intel_drivers`: contains everything from the
    base container + pre-installed Intel drivers.
-   The image comes in three flavors/tags:
+   The image comes in four flavors/tags:
    * `latest`: Intel drivers are downloaded from release/tag and saved in
     dependencies.json. The drivers are tested/validated everytime we upgrade
     the driver.
    * `devigc`: Intel Graphics Compiler driver from github actions artifacts,
    other drivers are downloaded from release/tag and saved in dependencies.json.
    * `unstable`: Intel drivers are downloaded from release/latest.
    The drivers are installed as it is, not tested or validated.
+   * `alldeps`: Includes the same Intel drivers as `latest`, as well as the
+   development kits for NVidia/AMD from the `ubuntu2204_build` container.
 - `ghcr.io/intel/llvm/ubuntu2204_build`: has development kits installed for
    NVidia/AMD and can be used for building DPC++ compiler from source with all
    backends enabled or for end-to-end testing with HIP/CUDA on machines with