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[LIBCLC] Extend __CLC_NVVM_ATOMIC with generic AS (#7221)
The diffs don't show it very well, but this patch extends `__CLC_NVVM_ATOMIC` macro to generate one more overload, targetting a generic address space, while at it, it also fixes a mangled name used in the implementation of `__CLC_NVVM_ATOMIC_IMPL_SUBSTITUTION`.
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‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -72,62 +72,62 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
7272
} \
7373
}
7474

75-
#define __CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
76-
OP, NAME_MANGLED, ADDR_SPACE, \
77-
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
78-
_CLC_DECL TYPE \
79-
NAME_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
80-
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
81-
enum MemorySemanticsMask semantics, TYPE value) { \
82-
/* Semantics mask may include memory order, storage class and other info \
83-
Memory order is stored in the lowest 5 bits */ \
84-
unsigned int order = semantics & 0x1F; \
85-
switch (order) { \
86-
case None: \
87-
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
88-
ADDR_SPACE, ADDR_SPACE_NV, ) \
89-
break; \
90-
case Acquire: \
91-
if (__clc_nvvm_reflect_arch() >= 700) { \
92-
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
93-
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
94-
} else { \
95-
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
96-
OP, ADDR_SPACE, ADDR_SPACE_NV) \
97-
} \
98-
break; \
99-
case Release: \
100-
if (__clc_nvvm_reflect_arch() >= 700) { \
101-
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
102-
ADDR_SPACE, ADDR_SPACE_NV, _release) \
103-
} else { \
104-
__spirv_MemoryBarrier(scope, Release); \
105-
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
106-
ADDR_SPACE, ADDR_SPACE_NV, ) \
107-
} \
108-
break; \
109-
case AcquireRelease: \
110-
if (__clc_nvvm_reflect_arch() >= 700) { \
111-
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
112-
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
113-
} else { \
114-
__spirv_MemoryBarrier(scope, Release); \
115-
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
116-
OP, ADDR_SPACE, ADDR_SPACE_NV) \
117-
} \
118-
break; \
119-
} \
120-
__builtin_trap(); \
121-
__builtin_unreachable(); \
75+
#define __CLC_NVVM_ATOMIC_IMPL( \
76+
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, NAME_MANGLED, \
77+
ADDR_SPACE, POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV, SUBSTITUTION) \
78+
__attribute__((always_inline)) _CLC_DECL TYPE \
79+
NAME_MANGLED##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv\
80+
5Scope4FlagENS##SUBSTITUTION##_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
81+
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
82+
enum MemorySemanticsMask semantics, TYPE value) { \
83+
/* Semantics mask may include memory order, storage class and other info \
84+
Memory order is stored in the lowest 5 bits */ \
85+
unsigned int order = semantics & 0x1F; \
86+
switch (order) { \
87+
case None: \
88+
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
89+
ADDR_SPACE, ADDR_SPACE_NV, ) \
90+
break; \
91+
case Acquire: \
92+
if (__clc_nvvm_reflect_arch() >= 700) { \
93+
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
94+
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
95+
} else { \
96+
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
97+
OP, ADDR_SPACE, ADDR_SPACE_NV) \
98+
} \
99+
break; \
100+
case Release: \
101+
if (__clc_nvvm_reflect_arch() >= 700) { \
102+
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
103+
ADDR_SPACE, ADDR_SPACE_NV, _release) \
104+
} else { \
105+
__spirv_MemoryBarrier(scope, Release); \
106+
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
107+
ADDR_SPACE, ADDR_SPACE_NV, ) \
108+
} \
109+
break; \
110+
case AcquireRelease: \
111+
if (__clc_nvvm_reflect_arch() >= 700) { \
112+
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
113+
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
114+
} else { \
115+
__spirv_MemoryBarrier(scope, Release); \
116+
__CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
117+
OP, ADDR_SPACE, ADDR_SPACE_NV) \
118+
} \
119+
break; \
120+
} \
121+
__builtin_trap(); \
122+
__builtin_unreachable(); \
122123
}
123124

124125
#define __CLC_NVVM_ATOMIC(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
125126
NAME_MANGLED) \
126-
__attribute__((always_inline)) \
127127
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
128-
NAME_MANGLED, __global, AS1, _global_) \
129-
__attribute__((always_inline)) \
130-
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
131-
NAME_MANGLED, __local, AS3, _shared_)
132-
128+
NAME_MANGLED, __global, PU3AS1, _global_, 1) \
129+
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
130+
NAME_MANGLED, __local, PU3AS3, _shared_, 1) \
131+
__CLC_NVVM_ATOMIC_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
132+
NAME_MANGLED, , P, _gen_, 0)
133133
#endif

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