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iclsrc
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Merge from 'sycl' to 'sycl-web'
2 parents aa4cd66 + c3a4076 commit d74f1aa

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‎.github/workflows/sycl_linux_build_and_test.yml

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -158,18 +158,11 @@ jobs:
158158
159159
- name: Pack toolchain
160160
run: tar -cJf llvm_sycl.tar.xz -C $GITHUB_WORKSPACE/build/install .
161-
- name: Pack LIT
162-
run: tar -cJf lit.tar.xz -C $GITHUB_WORKSPACE/src/llvm/utils/lit .
163161
- name: Upload toolchain
164162
uses: actions/upload-artifact@v3
165163
with:
166164
name: sycl_linux_${{ inputs.build_artifact_suffix }}
167165
path: llvm_sycl.tar.xz
168-
- name: Upload LIT
169-
uses: actions/upload-artifact@v3
170-
with:
171-
name: sycl_lit_${{ inputs.build_artifact_suffix }}
172-
path: lit.tar.xz
173166

174167
aws-start:
175168
name: Start AWS
@@ -239,8 +232,6 @@ jobs:
239232
test_ref: ${{ inputs.lts_ref }}
240233
sycl_artifact: sycl_linux_${{ inputs.build_artifact_suffix }}
241234
sycl_archive: llvm_sycl.tar.xz
242-
lit_artifact: sycl_lit_${{ inputs.build_artifact_suffix }}
243-
lit_archive: lit.tar.xz
244235
check_sycl_all: ${{ matrix.check_sycl_all }}
245236
results_name_suffix: ${{ matrix.config }}_${{ inputs.build_artifact_suffix }}
246237
cmake_args: '${{ matrix.cmake_args }} ${{ inputs.lts_cmake_extra_args }}'

‎clang/lib/Basic/Targets/NVPTX.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,8 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
169169
Builder.defineMacro("__PTX__");
170170
Builder.defineMacro("__NVPTX__");
171171
if (Opts.CUDAIsDevice || Opts.OpenMPIsDevice || Opts.SYCLIsDevice) {
172-
// Set __CUDA_ARCH__ for the GPU specified.
172+
// Set __CUDA_ARCH__ or __SYCL_CUDA_ARCH__ for the GPU specified.
173+
// The SYCL-specific macro is used to distinguish the SYCL and CUDA APIs.
173174
std::string CUDAArchCode = [this] {
174175
switch (GPU) {
175176
case CudaArch::GFX600:
@@ -260,7 +261,12 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
260261
}
261262
llvm_unreachable("unhandled CudaArch");
262263
}();
263-
Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
264+
265+
if (Opts.SYCLIsDevice) {
266+
Builder.defineMacro("__SYCL_CUDA_ARCH__", CUDAArchCode);
267+
} else {
268+
Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
269+
}
264270
}
265271
}
266272

‎clang/lib/Driver/Driver.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5674,7 +5674,7 @@ class OffloadingActionBuilder final {
56745674
// post link is not optional - even if not splitting, always need to
56755675
// process specialization constants
56765676
types::ID PostLinkOutType = isSPIR ? types::TY_Tempfiletable
5677-
: FullDeviceLinkAction->getType();
5677+
: types::TY_LLVM_BC;
56785678
auto createPostLinkAction = [&]() {
56795679
// For SPIR-V targets, force TY_Tempfiletable.
56805680
auto TypedPostLinkAction = C.MakeAction<SYCLPostLinkJobAction>(

‎clang/lib/Driver/ToolChains/SYCL.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -901,17 +901,14 @@ void SYCLToolChain::TranslateTargetOpt(const llvm::opt::ArgList &Args,
901901
OptNoTriple = A->getOption().matches(Opt);
902902
if (A->getOption().matches(Opt_EQ)) {
903903
// Passing device args: -X<Opt>=<triple> -opt=val.
904-
if (getDriver().MakeSYCLDeviceTriple(A->getValue()) != getTriple())
904+
StringRef GenDevice = SYCL::gen::resolveGenDevice(A->getValue());
905+
if (getDriver().MakeSYCLDeviceTriple(A->getValue()) != getTriple() &&
906+
GenDevice.empty())
905907
// Provided triple does not match current tool chain.
906908
continue;
907-
if (getTriple().isSPIR() &&
908-
getTriple().getSubArch() == llvm::Triple::SPIRSubArch_gen) {
909-
if (Device.empty() && StringRef(A->getValue()).startswith("intel_gpu"))
910-
continue;
911-
if (!Device.empty() &&
912-
getDriver().MakeSYCLDeviceTriple(A->getValue()) == getTriple())
913-
continue;
914-
}
909+
if (Device != GenDevice && getTriple().isSPIR() &&
910+
getTriple().getSubArch() == llvm::Triple::SPIRSubArch_gen)
911+
continue;
915912
} else if (!OptNoTriple)
916913
// Don't worry about any of the other args, we only want to pass what is
917914
// passed in -X<Opt>

‎clang/lib/Sema/SemaSYCL.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5392,9 +5392,12 @@ void SYCLIntegrationFooter::addVarDecl(const VarDecl *VD) {
53925392
// Note that isLocalVarDeclorParm excludes thread-local and static-local
53935393
// intentionally, as there is no way to 'spell' one of those in the
53945394
// specialization. We just don't generate the specialization for those, and
5395-
// let an error happen during host compilation.
5396-
if (!VD->hasGlobalStorage() || VD->isLocalVarDeclOrParm())
5395+
// let an error happen during host compilation. To avoid multiple entries for
5396+
// redeclarations, variables with external storage are omitted.
5397+
if (VD->hasLocalStorage() || VD->isLocalVarDeclOrParm() ||
5398+
VD->hasExternalStorage())
53975399
return;
5400+
53985401
// Step 3: Add to collection.
53995402
GlobalVars.push_back(VD);
54005403
}

‎clang/test/CodeGen/sycl-instrumentation-option.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
// RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_gen-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
66
// RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_fpga-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
77
// RUN: %clang_cc1 -fsycl-instrument-device-code -triple spir64_x86_64-unknown-unknown %s -emit-llvm -o - 2>&1 | FileCheck %s
8-
// CHECK-NOT: error
8+
// CHECK-NOT: error:
99

1010
// RUN: not %clang_cc1 -fsycl-instrument-device-code -triple spirv32 -emit-llvm %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-ERR
1111
// RUN: not %clang_cc1 -fsycl-instrument-device-code -triple spirv64 -emit-llvm %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-ERR

‎clang/test/CodeGenSYCL/device_global_int_footer_header.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,13 @@ int main() {
5252
// CHECK-FOOTER-NEXT: namespace {
5353
// CHECK-FOOTER-NEXT: __sycl_device_global_registration::__sycl_device_global_registration() noexcept {
5454

55+
extern device_global<int> Basic;
5556
device_global<int> Basic;
5657
// CHECK-FOOTER-NEXT: device_global_map::add((void *)&::Basic, "_Z5Basic");
58+
// CHECK-FOOTER-NOT: Basic
59+
60+
extern device_global<int> ExternDevGlobal;
61+
// CHECK-FOOTER-NOT: ExternDevGlobal
5762

5863
struct Wrapper {
5964
static device_global<int> WrapperDevGlobal;

‎clang/test/Driver/sycl-hip-no-rdc.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
// Test for -fno-sycl-rdc with HIP to make sure sycl-post-link is marked as outputting ir
2+
3+
// RUN: touch %t1.cpp
4+
// RUN: %clang -### -fsycl -fno-sycl-rdc -fsycl-targets=amdgcn-amd-amdhsa -Xsycl-target-backend=amdgcn-amd-amdhsa --offload-arch=gfx1031 --sysroot=%S/Inputs/SYCL %t1.cpp 2>&1 -ccc-print-phases | FileCheck %s
5+
6+
// CHECK: sycl-post-link, {{{.*}}}, ir, (device-sycl, gfx1031)

‎clang/test/Driver/sycl-oneapi-gpu.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -382,3 +382,16 @@
382382
// CHECK_PHASES_MIX: 26: file-table-tform, {22, 25}, tempfiletable, (device-sycl)
383383
// CHECK_PHASES_MIX: 27: clang-offload-wrapper, {26}, object, (device-sycl)
384384
// CHECK_PHASES_MIX: 28: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_gen-unknown-unknown:skl)" {20}, "device-sycl (spir64_gen-unknown-unknown)" {27}, image
385+
386+
/// Check that ocloc backend option settings only occur for the expected
387+
/// toolchains when mixing spir64_gen and intel_gpu
388+
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_dg1,spir64_gen,intel_gpu_skl \
389+
// RUN: -Xsycl-target-backend=spir64_gen "-device skl -DSKL" \
390+
// RUN: -Xsycl-target-backend=intel_gpu_dg1 "-DDG1" \
391+
// RUN: -Xsycl-target-backend=intel_gpu_skl "-DSKL2" \
392+
// RUN: -fno-sycl-device-lib=all -fno-sycl-instrument-device-code \
393+
// RUN: -target x86_64-unknown-linux-gnu -### %s 2>&1 | \
394+
// RUN: FileCheck %s --check-prefix=CHECK_TOOLS_BEOPTS
395+
// CHECK_TOOLS_BEOPTS: ocloc{{.*}} "-device" "dg1" "-DDG1"
396+
// CHECK_TOOLS_BEOPTS: ocloc{{.*}} "-device" "skl" "-DSKL"
397+
// CHECK_TOOLS_BEOPTS: ocloc{{.*}} "-device" "skl" "-DSKL2"

‎clang/test/Preprocessor/sycl-macro.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
// CHECK-NO-SYCL_FIT_IN_INT-NOT:#define __SYCL_ID_QUERIES_FIT_IN_INT__ 1
3434
// CHECK-SYCL-ID:#define __SYCL_ID_QUERIES_FIT_IN_INT__ 1
3535

36-
// CHECK-CUDA:#define __CUDA_ARCH__ 800
36+
// CHECK-CUDA:#define __SYCL_CUDA_ARCH__ 800
37+
// CHECK-CUDA-NOT:#define __CUDA_ARCH__ 800
3738

3839
// CHECK-HIP:#define __CUDA_ARCH__ 0

‎devops/actions/llvm_test_suite/action.yml

Lines changed: 10 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,6 @@ inputs:
1212
description: 'Name of SYCL toolchain archive file'
1313
required: false
1414
default: 'llvm_sycl.tar.xz'
15-
lit_artifact:
16-
description: 'Name of the artifact, that contains LIT tool'
17-
required: true
18-
lit_archive:
19-
description: 'Name of LIT archive file'
20-
required: false
21-
default: 'lit.tar.xz'
2215
results_name_suffix:
2316
description: 'Name suffix of the results artifact'
2417
required: true
@@ -55,24 +48,14 @@ runs:
5548
mkdir toolchain
5649
tar -xf ${{ inputs.sycl_archive }} -C toolchain
5750
rm -f ${{ inputs.sycl_archive }}
58-
- name: Download LIT
59-
uses: actions/download-artifact@v3
60-
with:
61-
name: ${{ inputs.lit_artifact }}
62-
- name: Extract LIT
63-
shell: bash
64-
run: |
65-
mkdir lit
66-
ls -la
67-
tar -xf ${{ inputs.lit_archive }} -C lit
68-
rm -f ${{ inputs.lit_archive }}
6951
- name: Configure
7052
shell: bash
7153
run: |
7254
echo "::group::CMake configuration"
73-
mkdir build
7455
export PATH=$PWD/toolchain/bin/:$PATH
75-
cmake -GNinja -B./build -S./llvm_test_suite -DTEST_SUITE_SUBDIRS=SYCL -DCHECK_SYCL_ALL="${{ inputs.check_sycl_all }}" -DCMAKE_CXX_COMPILER="$PWD/toolchain/bin/clang++" -DTEST_SUITE_LIT="$PWD/lit/lit.py" ${{ inputs.cmake_args }}
56+
# TODO: Rename check_sycl_all input
57+
cmake -GNinja -B./build-e2e -S./llvm/sycl/test-e2e -DSYCL_TEST_E2E_TARGETS="${{ inputs.check_sycl_all }}" -DCMAKE_CXX_COMPILER="$PWD/toolchain/bin/clang++" -DLLVM_LIT="$PWD/llvm/llvm/utils/lit/lit.py" ${{ inputs.cmake_args }}
58+
cmake -GNinja -B./build -S./llvm_test_suite -DTEST_SUITE_SUBDIRS=SYCL -DCHECK_SYCL_ALL="${{ inputs.check_sycl_all }}" -DCMAKE_CXX_COMPILER="$PWD/toolchain/bin/clang++" -DTEST_SUITE_LIT="$PWD/llvm/llvm/utils/lit/lit.py" ${{ inputs.cmake_args }}
7659
echo "::endgroup::"
7760
- name: Run testing
7861
shell: bash
@@ -102,8 +85,12 @@ runs:
10285
echo $LD_LIBRARY_PATH
10386
SYCL_PI_TRACE=-1 sycl-ls
10487
echo "::endgroup::"
105-
cd build
106-
ninja check-sycl-all
88+
echo "::group::SYCL In-Tree End-to-End tests"
89+
ninja -C build-e2e check-sycl-e2e
90+
echo "::endgroup::"
91+
echo "::group::LLVM Test Suite SYCL tests"
92+
ninja -C build check-sycl-all
93+
echo "::endgroup::"
10794
- name: Upload test results
10895
uses: actions/upload-artifact@v1
10996
if: always()
@@ -115,6 +102,6 @@ runs:
115102
if: always()
116103
run: |
117104
rm -rf toolchain
118-
rm -rf lit
119105
rm -rf build
106+
rm -rf build-e2e
120107
rm -rf llvm_test_suite

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 28 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1488,9 +1488,12 @@ LLVMToSPIRVBase::getLoopControl(const BranchInst *Branch,
14881488
// PartialCount must not be used with the DontUnroll bit
14891489
else if (S == "llvm.loop.unroll.count" &&
14901490
!(LoopControl & LoopControlDontUnrollMask)) {
1491-
size_t I = getMDOperandAsInt(Node, 1);
1492-
ParametersToSort.emplace_back(spv::LoopControlPartialCountMask, I);
1493-
LoopControl |= spv::LoopControlPartialCountMask;
1491+
if (BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_4)) {
1492+
BM->setMinSPIRVVersion(VersionNumber::SPIRV_1_4);
1493+
size_t I = getMDOperandAsInt(Node, 1);
1494+
ParametersToSort.emplace_back(spv::LoopControlPartialCountMask, I);
1495+
LoopControl |= spv::LoopControlPartialCountMask;
1496+
}
14941497
} else if (S == "llvm.loop.ivdep.enable")
14951498
LoopControl |= spv::LoopControlDependencyInfiniteMask;
14961499
else if (S == "llvm.loop.ivdep.safelen") {
@@ -2653,10 +2656,10 @@ bool LLVMToSPIRVBase::transDecoration(Value *V, SPIRVValue *BV) {
26532656

26542657
if (auto BVO = dyn_cast_or_null<OverflowingBinaryOperator>(V)) {
26552658
if (BVO->hasNoSignedWrap()) {
2656-
BV->setNoSignedWrap(true);
2659+
BV->setNoIntegerDecorationWrap<DecorationNoSignedWrap>(true);
26572660
}
26582661
if (BVO->hasNoUnsignedWrap()) {
2659-
BV->setNoUnsignedWrap(true);
2662+
BV->setNoIntegerDecorationWrap<DecorationNoUnsignedWrap>(true);
26602663
}
26612664
}
26622665

@@ -4963,22 +4966,19 @@ bool LLVMToSPIRVBase::transExecutionMode() {
49634966
}
49644967
} break;
49654968
case spv::ExecutionModeNoGlobalOffsetINTEL: {
4966-
if (BM->isAllowedToUseExtension(
4967-
ExtensionID::SPV_INTEL_kernel_attributes)) {
4968-
BF->addExecutionMode(BM->add(
4969-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
4970-
BM->addExtension(ExtensionID::SPV_INTEL_kernel_attributes);
4971-
BM->addCapability(CapabilityKernelAttributesINTEL);
4972-
}
4969+
if (!BM->isAllowedToUseExtension(
4970+
ExtensionID::SPV_INTEL_kernel_attributes))
4971+
break;
4972+
BF->addExecutionMode(BM->add(
4973+
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
4974+
BM->addExtension(ExtensionID::SPV_INTEL_kernel_attributes);
4975+
BM->addCapability(CapabilityKernelAttributesINTEL);
49734976
} break;
49744977
case spv::ExecutionModeVecTypeHint:
49754978
case spv::ExecutionModeSubgroupSize:
4976-
case spv::ExecutionModeSubgroupsPerWorkgroup: {
4977-
unsigned X;
4978-
N.get(X);
4979-
BF->addExecutionMode(BM->add(
4980-
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode), X)));
4981-
} break;
4979+
case spv::ExecutionModeSubgroupsPerWorkgroup:
4980+
AddSingleArgExecutionMode(static_cast<ExecutionMode>(EMode));
4981+
break;
49824982
case spv::ExecutionModeNumSIMDWorkitemsINTEL:
49834983
case spv::ExecutionModeSchedulerTargetFmaxMhzINTEL:
49844984
case spv::ExecutionModeMaxWorkDimINTEL:
@@ -4993,10 +4993,7 @@ bool LLVMToSPIRVBase::transExecutionMode() {
49934993
case spv::ExecutionModeSharedLocalMemorySizeINTEL: {
49944994
if (!BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
49954995
break;
4996-
unsigned SLMSize;
4997-
N.get(SLMSize);
4998-
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
4999-
BF, static_cast<ExecutionMode>(EMode), SLMSize)));
4996+
AddSingleArgExecutionMode(static_cast<ExecutionMode>(EMode));
50004997
} break;
50014998
case spv::ExecutionModeNamedBarrierCountINTEL: {
50024999
if (!BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
@@ -5014,12 +5011,14 @@ bool LLVMToSPIRVBase::transExecutionMode() {
50145011
case spv::ExecutionModeSignedZeroInfNanPreserve:
50155012
case spv::ExecutionModeRoundingModeRTE:
50165013
case spv::ExecutionModeRoundingModeRTZ: {
5017-
if (!BM->isAllowedToUseExtension(ExtensionID::SPV_KHR_float_controls))
5018-
break;
5019-
unsigned TargetWidth;
5020-
N.get(TargetWidth);
5021-
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
5022-
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
5014+
if (BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_4)) {
5015+
BM->setMinSPIRVVersion(VersionNumber::SPIRV_1_4);
5016+
AddSingleArgExecutionMode(static_cast<ExecutionMode>(EMode));
5017+
} else if (BM->isAllowedToUseExtension(
5018+
ExtensionID::SPV_KHR_float_controls)) {
5019+
BM->addExtension(ExtensionID::SPV_KHR_float_controls);
5020+
AddSingleArgExecutionMode(static_cast<ExecutionMode>(EMode));
5021+
}
50235022
} break;
50245023
case spv::ExecutionModeRoundingModeRTPINTEL:
50255024
case spv::ExecutionModeRoundingModeRTNINTEL:
@@ -5028,10 +5027,7 @@ bool LLVMToSPIRVBase::transExecutionMode() {
50285027
if (!BM->isAllowedToUseExtension(
50295028
ExtensionID::SPV_INTEL_float_controls2))
50305029
break;
5031-
unsigned TargetWidth;
5032-
N.get(TargetWidth);
5033-
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
5034-
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
5030+
AddSingleArgExecutionMode(static_cast<ExecutionMode>(EMode));
50355031
} break;
50365032
case spv::internal::ExecutionModeFastCompositeKernelINTEL: {
50375033
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite))

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVDecorate.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,8 @@ class SPIRVDecorateGeneric : public SPIRVAnnotationGeneric {
9494

9595
case DecorationMaxByteOffset:
9696
return static_cast<SPIRVWord>(VersionNumber::SPIRV_1_1);
97+
case DecorationUserSemantic:
98+
return static_cast<SPIRVWord>(VersionNumber::SPIRV_1_4);
9799

98100
default:
99101
return static_cast<SPIRVWord>(VersionNumber::SPIRV_1_0);
@@ -127,9 +129,6 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
127129

128130
std::optional<ExtensionID> getRequiredExtension() const override {
129131
switch (static_cast<size_t>(Dec)) {
130-
case DecorationNoSignedWrap:
131-
case DecorationNoUnsignedWrap:
132-
return ExtensionID::SPV_KHR_no_integer_wrap_decoration;
133132
case DecorationRegisterINTEL:
134133
case DecorationMemoryINTEL:
135134
case DecorationNumbanksINTEL:

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -845,12 +845,6 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability> {
845845

846846
std::optional<ExtensionID> getRequiredExtension() const override {
847847
switch (static_cast<unsigned>(Kind)) {
848-
case CapabilityDenormPreserve:
849-
case CapabilityDenormFlushToZero:
850-
case CapabilitySignedZeroInfNanPreserve:
851-
case CapabilityRoundingModeRTE:
852-
case CapabilityRoundingModeRTZ:
853-
return ExtensionID::SPV_KHR_float_controls;
854848
case CapabilityRoundToInfinityINTEL:
855849
case CapabilityFloatingPointModeINTEL:
856850
case CapabilityFunctionFloatControlINTEL:

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