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196 | 196 | // CHK-FPGA-AOCO-PHASES: 10: linker, {0, 9}, image, (host-sycl)
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197 | 197 | // CHK-FPGA-AOCO-PHASES: 11: compiler, {4}, ir, (device-sycl)
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198 | 198 | // CHK-FPGA-AOCO-PHASES: 12: input, "[[INPUTA]]", archive
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199 |
| -// CHK-FPGA-AOCO-PHASES-LIN: 13: clang-offload-unbundler, {12}, object |
| 199 | +// CHK-FPGA-AOCO-PHASES-LIN: 13: clang-offload-unbundler, {9, 12}, object |
200 | 200 | // CHK-FPGA-AOCO-PHASES-WIN: 13: clang-offload-unbundler, {12}, archive
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201 | 201 | // CHK-FPGA-AOCO-PHASES: 14: linker, {11, 13}, ir, (device-sycl)
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202 | 202 | // CHK-FPGA-AOCO-PHASES: 15: llvm-spirv, {14}, spirv, (device-sycl)
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211 | 211 | // RUN: %clang_cl -fsycl -fintelfpga -foffload-static-lib=%t_aoco.a -### %s 2>&1 \
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212 | 212 | // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-WIN %s
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213 | 213 | // CHK-FPGA-AOCO-LIN: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-check-section"
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214 |
| -// CHK-FPGA-AOCO-LIN: ld{{.*}} "-r" "-o" "[[PARTLINKOBJ:.+\.o]]" "{{.*}}crt1.o" "{{.*}}crti.o" "[[INPUTLIB]]" "{{.*}}crtn.o" |
| 214 | +// CHK-FPGA-AOCO-LIN: ld{{.*}} "-r" "-o" "[[PARTLINKOBJ:.+\.o]]" "{{.*}}crt1.o" "{{.*}}crti.o" "{{.*}}.o" "[[INPUTLIB]]" "{{.*}}crtn.o" |
215 | 215 | // CHK-FPGA-AOCO-LIN: clang-offload-bundler{{.*}} "-type=oo" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[PARTLINKOBJ]]" "-outputs={{.*}}" "-unbundle"
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216 | 216 | // CHK-FPGA-AOCO-WIN: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice-coff" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs={{.*}}" "-unbundle"
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217 | 217 | // CHK-FPGA-AOCO: llvm-link{{.*}} "@{{.*}}" "-o" "[[LINKEDBC:.+\.bc]]"
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