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| 1 | +:extension_name: SPV_INTEL_tensor_float32_conversion |
| 2 | +:capability_tf32_conversion_name: TensorFloat32ConversionINTEL |
| 3 | +:capability_tf32_conversion_token: 6425 |
| 4 | +:ConvertFToTF32_name: OpConvertFToTF32INTEL |
| 5 | +:ConvertFToTF32_token: 6426 |
| 6 | + |
| 7 | +{extension_name} |
| 8 | +================ |
| 9 | + |
| 10 | +== Name Strings |
| 11 | + |
| 12 | +{extension_name} |
| 13 | + |
| 14 | +== Contact |
| 15 | + |
| 16 | +To report problems with this extension, please open a new issue at: |
| 17 | + |
| 18 | +https://github.com/intel/llvm |
| 19 | + |
| 20 | +== Contributors |
| 21 | + |
| 22 | +- Dmitry Sidorov, Intel + |
| 23 | +- Victor Mustya, Intel + |
| 24 | +- Kacper Kasper, Intel + |
| 25 | +- Ben Ashbaugh, Intel + |
| 26 | + |
| 27 | +== Notice |
| 28 | + |
| 29 | +Copyright (c) 2022 Intel Corporation. All rights reserved. |
| 30 | + |
| 31 | +== Status |
| 32 | + |
| 33 | +Working Draft |
| 34 | + |
| 35 | +This is a preview extension specification, intended to provide early access to a |
| 36 | +feature for review and community feedback. When the feature matures, this |
| 37 | +specification may be released as a formal extension. |
| 38 | + |
| 39 | + |
| 40 | +Because the interfaces defined by this specification are not final and are |
| 41 | +subject to change they are not intended to be used by shipping software |
| 42 | +products. If you are interested in using this feature in your software product, |
| 43 | +please let us know! |
| 44 | + |
| 45 | +== Version |
| 46 | + |
| 47 | +[width="40%",cols="25,25"] |
| 48 | +|======================================== |
| 49 | +| Last Modified Date | {docdate} |
| 50 | +| Revision | 1 |
| 51 | +|======================================== |
| 52 | + |
| 53 | +== Dependencies |
| 54 | + |
| 55 | +This extension is written against the SPIR-V Specification, |
| 56 | +Version 1.6 Revision 2. |
| 57 | + |
| 58 | +This extension requires SPIR-V 1.0. |
| 59 | + |
| 60 | +== Overview |
| 61 | + |
| 62 | +This extension adds conversion instruction from float to tensor float (TF32) |
| 63 | +data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a |
| 64 | +fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead |
| 65 | +instruction below uses 32-bit float type to represent TF32 value. |
| 66 | + |
| 67 | + |
| 68 | +== Extension Name |
| 69 | + |
| 70 | + |
| 71 | +To use this extension within a SPIR-V module, the appropriate *OpExtension* must |
| 72 | +be present in the module: |
| 73 | + |
| 74 | +[subs="attributes"] |
| 75 | +---- |
| 76 | +OpExtension "{extension_name}" |
| 77 | +---- |
| 78 | + |
| 79 | +== New Capabilities |
| 80 | + |
| 81 | +This extension introduces new capabilities: |
| 82 | + |
| 83 | +[subs="attributes"] |
| 84 | +---- |
| 85 | +{capability_tf32_conversion_name} |
| 86 | +---- |
| 87 | + |
| 88 | +== New Instructions |
| 89 | + |
| 90 | +Instructions added under the *{capability_tf32_conversion_name}* capability: |
| 91 | + |
| 92 | +[subs="attributes"] |
| 93 | +---- |
| 94 | +{ConvertFToTF32_name} |
| 95 | +---- |
| 96 | + |
| 97 | + |
| 98 | +== Token Number Assignments |
| 99 | + |
| 100 | +[width="40%"] |
| 101 | +[cols="70%,30%"] |
| 102 | +[grid="rows"] |
| 103 | +|==== |
| 104 | +|*{capability_tf32_conversion_name}* | {capability_tf32_conversion_token} |
| 105 | +|{ConvertFToTF32_name} | {ConvertFToTF32_token} |
| 106 | +|==== |
| 107 | + |
| 108 | +== Modifications to the SPIR-V Specification, Version 1.6 |
| 109 | + |
| 110 | +=== Capabilities |
| 111 | + |
| 112 | +Modify Section 3.31, Capability, adding rows to the Capability table: |
| 113 | + |
| 114 | +-- |
| 115 | +[options="header"] |
| 116 | +|==== |
| 117 | +2+^| Capability ^| Implicitly Declares |
| 118 | +| {capability_tf32_conversion_token} | *{capability_tf32_conversion_name}* |
| 119 | +| Enables a rounding instruction from float to tf32 data format + |
| 120 | + + |
| 121 | +See also extension: *{extension_name}* |
| 122 | +|==== |
| 123 | +-- |
| 124 | + |
| 125 | + |
| 126 | +=== Instructions |
| 127 | + |
| 128 | +==== 3.37.11. Conversion Instructions |
| 129 | + |
| 130 | +[cols="1,1,3*3",width="100%"] |
| 131 | +|===== |
| 132 | +4+|[[OpConvertFToTF32]]*{ConvertFToTF32_name}* + |
| 133 | + + |
| 134 | +Convert value numerically from a floating point type to *TF32*. |
| 135 | +It rounds up 13th bit of a float value and zero out last 13 bits. + |
| 136 | + + |
| 137 | +'Result Type' must be a scalar or vector of floating-point type. + |
| 138 | + + |
| 139 | +'Float Value' must be a scalar or vector of floating-point type. |
| 140 | +It must have the same number of components as Result Type. + |
| 141 | + + |
| 142 | +Results are computed per component. + |
| 143 | + + |
| 144 | +1+|Capability: + |
| 145 | +*{capability_tf32_conversion_name}* |
| 146 | +1+| 4 | {ConvertFToTF32_token} |
| 147 | +| '<id>' + |
| 148 | +'Result Type' |
| 149 | +| 'Result <id>' |
| 150 | +| '<id>' + |
| 151 | +'Float Value' |
| 152 | +| '<id>' + |
| 153 | +|===== |
| 154 | + |
| 155 | + |
| 156 | +== Issues |
| 157 | + |
| 158 | +// . first issue |
| 159 | +// + |
| 160 | +// -- |
| 161 | +// *RESOLVED*: |
| 162 | +// -- |
| 163 | + |
| 164 | +== Revision History |
| 165 | + |
| 166 | +[cols="5,15,15,70"] |
| 167 | +[grid="rows"] |
| 168 | +[options="header"] |
| 169 | +|======================================== |
| 170 | +|Rev|Date|Author|Changes |
| 171 | +|1|2022-08-22|Dmitry Sidorov|Initial revision |
| 172 | +|======================================== |
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