Skip to content

Commit f9b664b

Browse files
mdtoguchimdtoguchi
committed
[Driver][SYCL] Update behaviors to use new -fsycl-dead-args-optimization
Behavior is now off by default. Added support for -fsycl-dead-args-optimization to control enabling. Also updated tests to use option to exercise the optimization.
1 parent c0ae55b commit f9b664b

File tree

12 files changed

+84
-100
lines changed

12 files changed

+84
-100
lines changed

‎clang/include/clang/Driver/Options.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3551,7 +3551,12 @@ def fsycl_esimd : Flag<["-"], "fsycl-explicit-simd">, Group<sycl_Group>, Flags<[
35513551
def fno_sycl_esimd : Flag<["-"], "fno-sycl-explicit-simd">, Group<sycl_Group>,
35523552
HelpText<"Disable SYCL explicit SIMD extension">, Flags<[NoArgumentUnused, CoreOption]>;
35533553
defm sycl_early_optimizations : OptOutFFlag<"sycl-early-optimizations", "Enable", "Disable", " standard optimization pipeline for SYCL device compiler", [CoreOption]>;
3554-
3554+
def fsycl_dead_args_optimization : Flag<["-"], "fsycl-dead-args-optimization">,
3555+
Group<sycl_Group>, Flags<[NoArgumentUnused, CoreOption]>, HelpText<"Enables "
3556+
"elimination of DPC++ dead kernel arguments">;
3557+
def fno_sycl_dead_args_optimization : Flag<["-"], "fno-sycl-dead-args-optimization">,
3558+
Group<sycl_Group>, Flags<[NoArgumentUnused, CoreOption]>, HelpText<"Disables "
3559+
"elimination of DPC++ dead kernel arguments">;
35553560
//===----------------------------------------------------------------------===//
35563561
// CC1 Options
35573562
//===----------------------------------------------------------------------===//

‎clang/lib/Driver/Driver.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4111,8 +4111,9 @@ class OffloadingActionBuilder final {
41114111
WrapDeviceOnlyBinary = Args.hasArg(options::OPT_fsycl_link_EQ);
41124112
auto *DeviceCodeSplitArg =
41134113
Args.getLastArg(options::OPT_fsycl_device_code_split_EQ);
4114-
EnableDAE = Args.hasFlag(options::OPT_fsycl_early_optimizations,
4115-
options::OPT_fno_sycl_early_optimizations, true);
4114+
EnableDAE = Args.hasFlag(options::OPT_fsycl_dead_args_optimization,
4115+
options::OPT_fno_sycl_dead_args_optimization,
4116+
false);
41164117
// -fsycl-device-code-split is an alias to
41174118
// -fsycl-device-code-split=per_source
41184119
DeviceCodeSplit = DeviceCodeSplitArg &&

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4124,9 +4124,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
41244124
CmdArgs.push_back("-sycl-opt");
41254125
}
41264126
// Turn on Dead Parameter Elimination Optimization with early optimizations
4127-
if (Args.hasFlag(options::OPT_fsycl_early_optimizations,
4128-
options::OPT_fno_sycl_early_optimizations,
4129-
!RawTriple.isNVPTX()))
4127+
if (Args.hasFlag(options::OPT_fsycl_dead_args_optimization,
4128+
options::OPT_fno_sycl_dead_args_optimization, false))
41304129
CmdArgs.push_back("-fenable-sycl-dae");
41314130

41324131
// Pass the triple of host when doing SYCL
@@ -7813,9 +7812,8 @@ void SYCLPostLink::ConstructJob(Compilation &C, const JobAction &JA,
78137812
// -fsycl-device-code-split=per_source
78147813

78157814
// Turn on Dead Parameter Elimination Optimization with early optimizations
7816-
if (TCArgs.hasFlag(options::OPT_fsycl_early_optimizations,
7817-
options::OPT_fno_sycl_early_optimizations,
7818-
!getToolChain().getTriple().isNVPTX()))
7815+
if (TCArgs.hasFlag(options::OPT_fsycl_dead_args_optimization,
7816+
options::OPT_fno_sycl_dead_args_optimization, false))
78197817
addArgs(CmdArgs, TCArgs, {"-emit-param-info"});
78207818
if (JA.getType() == types::TY_LLVM_BC) {
78217819
// single file output requested - this means only perform necessary IR

‎clang/test/Driver/sycl-device-optimizations.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@
3030
// CHECK-NO-SYCL-EARLY-OPTS: "-fno-sycl-early-optimizations"
3131

3232
/// Check that Dead Parameter Elimination Optimization is enabled
33-
// RUN: %clang -### -fsycl %s 2>&1 \
33+
// RUN: %clang -### -fsycl -fsycl-dead-args-optimization %s 2>&1 \
3434
// RUN: | FileCheck -check-prefix=CHECK-DAE %s
35-
// RUN: %clang -### -fsycl -fsycl-early-optimizations %s 2>&1 \
35+
// RUN: %clang_cl -### -fsycl -fsycl-dead-args-optimization %s 2>&1 \
3636
// RUN: | FileCheck -check-prefix=CHECK-DAE %s
3737
// CHECK-DAE: clang{{.*}} "-fenable-sycl-dae"
3838
// CHECK-DAE: sycl-post-link{{.*}} "-emit-param-info"

‎clang/test/Driver/sycl-offload-intelfpga.cpp

Lines changed: 34 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,8 @@
3131
// CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle"
3232
// CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}}
3333
// CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
34-
// CHK-FPGA-LINK: sycl-post-link{{.*}} "-emit-param-info" "-symbols" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]"
35-
// CHK-FPGA-LINK: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT2_2:.+\.txt]]" "[[OUTPUT2]]"
36-
// CHK-FPGA-LINK: llvm-foreach{{.*}} "--in-file-list=[[OUTPUT2_2]]" {{.*}}llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_2]]"
34+
// CHK-FPGA-LINK: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
35+
// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
3736
// CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
3837
// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl"
3938
// CHK-FPGA-LINK: llvm-ar{{.*}} "cr" "libfoo.a" "[[INPUT]]"
@@ -58,9 +57,8 @@
5857
// CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle"
5958
// CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}}
6059
// CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]"
61-
// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-emit-param-info" "-symbols" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]"
62-
// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT2_2:.+\.txt]]" "[[OUTPUT2]]"
63-
// CHK-FPGA-LINK-WIN: llvm-foreach{{.*}} "--in-file-list=[[OUTPUT2_2]]" {{.*}}llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_2]]"
60+
// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]"
61+
// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]"
6462
// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl"
6563
// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[INPUT]]" {{.*}} "-OUT:libfoo.lib"
6664

@@ -204,14 +202,12 @@
204202
// CHK-FPGA-LINK-SRC: 9: linker, {8}, archive, (host-sycl)
205203
// CHK-FPGA-LINK-SRC: 10: compiler, {3}, ir, (device-sycl)
206204
// CHK-FPGA-LINK-SRC: 11: linker, {10}, ir, (device-sycl)
207-
// CHK-FPGA-LINK-SRC: 12: sycl-post-link, {11}, tempfiletable, (device-sycl)
208-
// CHK-FPGA-LINK-SRC: 13: file-table-tform, {12}, tempfilelist, (device-sycl)
209-
// CHK-FPGA-LINK-SRC: 14: llvm-spirv, {13}, tempfilelist, (device-sycl)
210-
// CHK-FPGA-LINK-SRC: 15: backend-compiler, {14}, fpga_aocr, (device-sycl)
211-
// CHK-FPGA-LINK-SRC: 16: file-table-tform, {12, 15}, tempfiletable, (device-sycl)
212-
// CHK-FPGA-LINK-SRC: 17: clang-offload-wrapper, {16}, object, (device-sycl)
213-
// CHK-FPGA-LINK-SRC-DEFAULT: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {17}, archive
214-
// CHK-FPGA-LINK-SRC-CL: 18: offload, "host-sycl (x86_64-pc-windows-msvc)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {17}, archive
205+
// CHK-FPGA-LINK-SRC: 12: sycl-post-link, {11}, ir, (device-sycl)
206+
// CHK-FPGA-LINK-SRC: 13: llvm-spirv, {12}, spirv, (device-sycl)
207+
// CHK-FPGA-LINK-SRC: 14: backend-compiler, {13}, fpga_aocr, (device-sycl)
208+
// CHK-FPGA-LINK-SRC: 15: clang-offload-wrapper, {14}, object, (device-sycl)
209+
// CHK-FPGA-LINK-SRC-DEFAULT: 16: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {15}, archive
210+
// CHK-FPGA-LINK-SRC-CL: 16: offload, "host-sycl (x86_64-pc-windows-msvc)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {15}, archive
215211

216212
/// -fintelfpga with -reuse-exe=
217213
// RUN: touch %t.cpp
@@ -287,14 +283,12 @@
287283
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 1: clang-offload-unbundler, {0}, object, (host-sycl)
288284
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 2: linker, {1}, image, (host-sycl)
289285
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 3: linker, {1}, ir, (device-sycl)
290-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 4: sycl-post-link, {3}, tempfiletable, (device-sycl)
291-
// CHK-FPGA-DEP-FILES-OBJ-PHASES 5: file-table-tform, {4}, tempfilelist, (device-sycl)
292-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 6: llvm-spirv, {5}, tempfilelist, (device-sycl)
293-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 7: clang-offload-unbundler, {0}, fpga_dependencies
294-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 8: backend-compiler, {6, 7}, fpga_aocx, (device-sycl)
295-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 9: file-table-tform, {4, 8}, tempfiletable, (device-sycl)
296-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 10: clang-offload-wrapper, {9}, object, (device-sycl)
297-
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 11: offload, "host-sycl (x86_64-{{unknown-linux-gnu|pc-windows-msvc}})" {2}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {10}, image
286+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 4: sycl-post-link, {3}, ir, (device-sycl)
287+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 5: llvm-spirv, {4}, spirv, (device-sycl)
288+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 6: clang-offload-unbundler, {0}, fpga_dependencies
289+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 7: backend-compiler, {5, 6}, fpga_aocx, (device-sycl)
290+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 8: clang-offload-wrapper, {7}, object, (device-sycl)
291+
// CHK-FPGA-DEP-FILES-OBJ-PHASES: 9: offload, "host-sycl (x86_64-{{unknown-linux-gnu|pc-windows-msvc}})" {2}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {8}, image
298292

299293
/// -fintelfpga output report file test
300294
// RUN: mkdir -p %t_dir
@@ -372,15 +366,13 @@
372366
// CHK-FPGA-AOCO-PHASES: 13: partial-link, {9, 12}, object
373367
// CHK-FPGA-AOCO-PHASES: 14: clang-offload-unbundler, {13}, object
374368
// CHK-FPGA-AOCO-PHASES: 15: linker, {11, 14}, ir, (device-sycl)
375-
// CHK-FPGA-AOCO-PHASES: 16: sycl-post-link, {15}, tempfiletable, (device-sycl)
376-
// CHK-FPGA-AOCO-PHASES: 17: file-table-tform, {16}, tempfilelist, (device-sycl)
377-
// CHK-FPGA-AOCO-PHASES: 18: llvm-spirv, {17}, tempfilelist, (device-sycl)
378-
// CHK-FPGA-AOCO-PHASES: 19: input, "[[INPUTA]]", fpga_aoco
379-
// CHK-FPGA-AOCO-PHASES: 20: clang-offload-unbundler, {19}, fpga_aoco
380-
// CHK-FPGA-AOCO-PHASES: 21: backend-compiler, {18, 20}, fpga_aocx, (device-sycl)
381-
// CHK-FPGA-AOCO-PHASES: 22: file-table-tform, {16, 21}, tempfiletable, (device-sycl)
382-
// CHK-FPGA-AOCO-PHASES: 23: clang-offload-wrapper, {22}, object, (device-sycl)
383-
// CHK-FPGA-AOCO-PHASES: 24: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {23}, image
369+
// CHK-FPGA-AOCO-PHASES: 16: sycl-post-link, {15}, ir, (device-sycl)
370+
// CHK-FPGA-AOCO-PHASES: 17: llvm-spirv, {16}, spirv, (device-sycl)
371+
// CHK-FPGA-AOCO-PHASES: 18: input, "[[INPUTA]]", fpga_aoco
372+
// CHK-FPGA-AOCO-PHASES: 19: clang-offload-unbundler, {18}, fpga_aoco
373+
// CHK-FPGA-AOCO-PHASES: 20: backend-compiler, {17, 19}, fpga_aocx, (device-sycl)
374+
// CHK-FPGA-AOCO-PHASES: 21: clang-offload-wrapper, {20}, object, (device-sycl)
375+
// CHK-FPGA-AOCO-PHASES: 22: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {21}, image
384376

385377
/// FPGA AOCO Windows phases check
386378
// RUN: %clang_cl -fsycl -fintelfpga -foffload-static-lib=%t_aoco_cl.a %s -### -ccc-print-phases 2>&1 \
@@ -400,15 +392,13 @@
400392
// CHK-FPGA-AOCO-PHASES-WIN: 12: input, "[[INPUTA:.+\.a]]", archive
401393
// CHK-FPGA-AOCO-PHASES-WIN: 13: clang-offload-unbundler, {12}, archive
402394
// CHK-FPGA-AOCO-PHASES-WIN: 14: linker, {11, 13}, ir, (device-sycl)
403-
// CHK-FPGA-AOCO-PHASES-WIN: 15: sycl-post-link, {14}, tempfiletable, (device-sycl)
404-
// CHK-FPGA-AOCO-PHASES-WIN: 16: file-table-tform, {15}, tempfilelist, (device-sycl)
405-
// CHK-FPGA-AOCO-PHASES-WIN: 17: llvm-spirv, {16}, tempfilelist, (device-sycl)
406-
// CHK-FPGA-AOCO-PHASES-WIN: 18: input, "[[INPUTA]]", fpga_aoco
407-
// CHK-FPGA-AOCO-PHASES-WIN: 19: clang-offload-unbundler, {18}, fpga_aoco
408-
// CHK-FPGA-AOCO-PHASES-WIN: 20: backend-compiler, {17, 19}, fpga_aocx, (device-sycl)
409-
// CHK-FPGA-AOCO-PHASES-WIN: 21: file-table-tform, {15, 20}, tempfiletable, (device-sycl)
410-
// CHK-FPGA-AOCO-PHASES-WIN: 22: clang-offload-wrapper, {21}, object, (device-sycl)
411-
// CHK-FPGA-AOCO-PHASES-WIN: 23: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {22}, image
395+
// CHK-FPGA-AOCO-PHASES-WIN: 15: sycl-post-link, {14}, ir, (device-sycl)
396+
// CHK-FPGA-AOCO-PHASES-WIN: 16: llvm-spirv, {15}, spirv, (device-sycl)
397+
// CHK-FPGA-AOCO-PHASES-WIN: 17: input, "[[INPUTA]]", fpga_aoco
398+
// CHK-FPGA-AOCO-PHASES-WIN: 18: clang-offload-unbundler, {17}, fpga_aoco
399+
// CHK-FPGA-AOCO-PHASES-WIN: 19: backend-compiler, {16, 18}, fpga_aocx, (device-sycl)
400+
// CHK-FPGA-AOCO-PHASES-WIN: 20: clang-offload-wrapper, {19}, object, (device-sycl)
401+
// CHK-FPGA-AOCO-PHASES-WIN: 21: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {20}, image
412402

413403
/// aoco test, checking tools
414404
// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -foffload-static-lib=%t_aoco.a -### %s 2>&1 \
@@ -425,13 +415,11 @@
425415
// CHK-FPGA-AOCO-LIN: clang-offload-bundler{{.*}} "-type=oo" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[PARTLINKOBJ]]" "-outputs={{.*}}" "-unbundle"
426416
// CHK-FPGA-AOCO-WIN: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs={{.*}}" "-unbundle"
427417
// CHK-FPGA-AOCO: llvm-link{{.*}} "@{{.*}}" "-o" "[[LINKEDBC:.+\.bc]]"
428-
// CHK-FPGA-AOCO: sycl-post-link{{.*}} "-emit-param-info" "-symbols" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.table]]" "[[LINKEDBC]]"
429-
// CHK-FPGA-AOCO: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT_TFORM:.+\.txt]]" "[[PLINKEDBC]]"
430-
// CHK-FPGA-AOCO: llvm-foreach{{.*}} "--in-file-list=[[OUTPUT_TFORM]]" {{.*}}llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.txt]]" {{.*}} "[[OUTPUT_TFORM]]"
418+
// CHK-FPGA-AOCO: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]"
419+
// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]"
431420
// CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle"
432-
// CHK-FPGA-AOCO: llvm-foreach{{.*}} "--in-file-list=[[TARGSPV]]"{{.*}}"--out-file-list=[[AOC_OUT:.+\.aocx]]" {{.*}}aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"
433-
// CHK-FPGA-AOCO: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[LAST_TABLE:.+\.table]]" "[[PLINKEDBC]]" "[[AOCXOUT]]"
434-
// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[LAST_TABLE]]"
421+
// CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl"
422+
// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCXOUT]]"
435423
// CHK-FPGA-AOCO-LIN: llc{{.*}} "-filetype=obj" "-o" "[[FINALOBJL:.+\.o]]" "[[FINALBC]]"
436424
// CHK-FPGA-AOCO-WIN: llc{{.*}} "-filetype=obj" "-o" "[[FINALOBJW:.+\.obj]]" "[[FINALBC]]"
437425
// CHK-FPGA-AOCO-LIN: ld{{.*}} "[[INPUTLIB]]" {{.*}} "[[FINALOBJL]]"

0 commit comments

Comments
 (0)