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[E2E Test] Add regression test for #13887 (#13888)
The test is marked as `XFAIL` until #13887 gets fixed in OCL FPGA EMU. Signed-off-by: Yilong Guo <[email protected]>
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//===-- fpga_pipes_mixed_usage.cpp -- Using pipe and experimental::pipe ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// REQUIRES: accelerator
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// RUN: %{build} -o %t.out
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// RUN: %{run} %t.out
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// https://github.com/intel/llvm/issues/13887
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// XFAIL: *
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// If users need to use host pipe feature provided by experimental::pipe, all
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// pipes in their design should use the experimental::pipe (as a workround).
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#include <iostream>
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#include <sycl/detail/core.hpp>
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#include <sycl/ext/intel/fpga_extensions.hpp>
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#include <sycl/pipes.hpp>
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// Test for using sycl::ext::intel::pipe and
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// sycl::ext::intel::experimental::pipe in the same kernel.
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using NonExpPipe = sycl::ext::intel::pipe<class PipeA, int>;
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using ExpPipe = sycl::ext::intel::experimental::pipe<class PipeB, short>;
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int main() {
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sycl::queue q(sycl::ext::intel::fpga_emulator_selector_v);
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q.submit([&](sycl::handler &cgh) {
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cgh.single_task<class SimplePipeWrite>([=]() {
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NonExpPipe::write(42);
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ExpPipe::write(24);
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});
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});
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q.wait();
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int a = 0;
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short b = 0;
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sycl::buffer<int, 1> buf_a(&a, 1);
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sycl::buffer<short, 1> buf_b(&b, 1);
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q.submit([&](sycl::handler &cgh) {
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auto acc_a = buf_a.get_access<sycl::access::mode::write>(cgh);
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auto acc_b = buf_b.get_access<sycl::access::mode::write>(cgh);
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cgh.single_task<class SimplePipeRead>([=]() {
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acc_a[0] = NonExpPipe::read();
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acc_b[0] = ExpPipe::read();
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});
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});
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q.wait();
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if (a != 42 || b != 24) {
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std::cout << "Failed\n";
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return 1;
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}
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std::cout << "Passed\n";
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return 0;
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}

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