[PowerPC] add RUN lines for both endians to test; NFC

The load narrowing transform works for both targets,
so we might as well test both with simple examples
like this.

Author: rotateright

llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll

@@ -1,18 +1,18 @@
-; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64--   < %s | FileCheck %s --check-prefixes=BE
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s --check-prefixes=LE
 
-; Function Attrs: nounwind readonly
-define signext i32 @test(i32* nocapture readonly %P) #0 {
-entry:
-  %0 = load i32, i32* %P, align 4
-  %shr = lshr i32 %0, 24
+define signext i32 @test(i32* nocapture readonly %P) nounwind {
+; BE-LABEL: test:
+; BE:       # %bb.0:
+; BE-NEXT:    lbz r3, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test:
+; LE:       # %bb.0:
+; LE-NEXT:    lbz r3, 3(r3)
+; LE-NEXT:    blr
+  %t0 = load i32, i32* %P, align 4
+  %shr = lshr i32 %t0, 24
   ret i32 %shr
-
-; CHECK-LABEL: @test
-; CHECK: lbz 3, 0(3)
-; CHECK: blr
 }
-
-attributes #0 = { nounwind readonly }
-