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iclsrc
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Merge from 'sycl' to 'sycl-web' (7 commits)
2 parents 4cf5269 + ce7725d commit feac4ca

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12 files changed

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12 files changed

+252
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‎buildbot/dependency.conf

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2021.12.6.0.19
44
# https://github.com/intel/llvm/releases/download/2021-WW26/win-oclcpuexp-2021.12.6.0.19_rel.zip
55
ocl_cpu_rt_ver_win=2021.12.6.0.19
66
# Same GPU driver supports Level Zero and OpenCL
7-
# https://github.com/intel/compute-runtime/releases/tag/21.34.20767
8-
ocl_gpu_rt_ver=21.34.20767
7+
# https://github.com/intel/compute-runtime/releases/tag/21.37.20939
8+
ocl_gpu_rt_ver=21.37.20939
99
# Same GPU driver supports Level Zero and OpenCL
1010
# https://downloadmirror.intel.com/648245/igfx_win_100.9864.zip
1111
ocl_gpu_rt_ver_win=30.0.100.9864
@@ -30,7 +30,7 @@ ocloc_ver_win=27.20.100.9168
3030
[DRIVER VERSIONS]
3131
cpu_driver_lin=2021.12.6.0.19
3232
cpu_driver_win=2021.12.6.0.19
33-
gpu_driver_lin=21.34.20767
33+
gpu_driver_lin=21.37.20939
3434
gpu_driver_win=30.0.100.9864
3535
fpga_driver_lin=2021.12.6.0.19
3636
fpga_driver_win=2021.12.6.0.19

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8720,11 +8720,7 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
87208720
TranslatorArgs.push_back(Output.getFilename());
87218721
if (JA.isDeviceOffloading(Action::OFK_SYCL)) {
87228722
TranslatorArgs.push_back("-spirv-max-version=1.4");
8723-
// TODO: align debug info for FPGA H/W when its SPIR-V consumer is ready
8724-
if (C.getDriver().isFPGAEmulationMode())
8725-
TranslatorArgs.push_back("-spirv-debug-info-version=ocl-100");
8726-
else
8727-
TranslatorArgs.push_back("-spirv-debug-info-version=legacy");
8723+
TranslatorArgs.push_back("-spirv-debug-info-version=ocl-100");
87288724
// Prevent crash in the translator if input IR contains DIExpression
87298725
// operations which don't have mapping to OpenCL.DebugInfo.100 spec.
87308726
TranslatorArgs.push_back("-spirv-allow-extra-diexpressions");

‎clang/lib/Driver/ToolChains/SYCL.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -66,10 +66,7 @@ const char *SYCL::Linker::constructLLVMSpirvCommand(
6666
} else {
6767
CmdArgs.push_back("-spirv-max-version=1.4");
6868
CmdArgs.push_back("-spirv-ext=+all");
69-
if (!C.getDriver().isFPGAEmulationMode())
70-
CmdArgs.push_back("-spirv-debug-info-version=legacy");
71-
else
72-
CmdArgs.push_back("-spirv-debug-info-version=ocl-100");
69+
CmdArgs.push_back("-spirv-debug-info-version=ocl-100");
7370
CmdArgs.push_back("-spirv-allow-extra-diexpressions");
7471
CmdArgs.push_back("-spirv-allow-unknown-intrinsics=llvm.genx.");
7572
CmdArgs.push_back("-o");

‎clang/test/Driver/sycl-offload.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -704,8 +704,7 @@
704704
// CHK-TOOLS-AOT: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT2_1:.+\.txt]]" "[[OUTPUT2_T]]"
705705
// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.4" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
706706
// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.4" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
707-
// CHK-TOOLS-FPGA-HW: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.4" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
708-
// CHK-TOOLS-FPGA-EMU: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.4" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
707+
// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.4" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
709708
// CHK-TOOLS-FPGA-HW: aoc{{.*}} "-o" "[[OUTPUT4_T:.+\.aocx]]" "[[OUTPUT3_T]]"
710709
// CHK-TOOLS-FPGA-EMU: opencl-aot{{.*}} "-spv=[[OUTPUT3_T]]" "-ir=[[OUTPUT4_T:.+\.aocx]]"
711710
// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4_T:.+\.out]]" {{.*}} "[[OUTPUT3_T]]"

‎libclc/ptx-nvidiacl/libspirv/images/image.cl

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -973,7 +973,7 @@ _CLC_DEFINE_IMAGE_SAMPLED_READ_BUILTIN(half, DF16_, 3, int4, Dv4_i, float4)
973973
#undef _CLC_DEFINE_IMAGE_SAMPLED_READ_BUILTIN
974974

975975
// Size Queries
976-
_CLC_DECL int _Z22__spirv_ImageQuerySizeIDv2_i14ocl_image1d_roET_T0_(
976+
_CLC_DECL int _Z22__spirv_ImageQuerySizeIDv1_i14ocl_image1d_roET_T0_(
977977
read_only image1d_t image) {
978978
return __nvvm_suq_width_1i(image);
979979
}
@@ -985,10 +985,10 @@ _CLC_DECL int2 _Z22__spirv_ImageQuerySizeIDv2_i14ocl_image2d_roET_T0_(
985985
return (int2)(width, height);
986986
}
987987

988-
_CLC_DECL int4 _Z22__spirv_ImageQuerySizeIDv2_i14ocl_image3d_roET_T0_(
988+
_CLC_DECL int3 _Z22__spirv_ImageQuerySizeIDv3_i14ocl_image3d_roET_T0_(
989989
read_only image3d_t image) {
990990
int width = __nvvm_suq_width_3i(image);
991991
int height = __nvvm_suq_height_3i(image);
992992
int depth = __nvvm_suq_depth_3i(image);
993-
return (int4)(width, height, depth, 0);
993+
return (int3)(width, height, depth);
994994
}

‎sycl/doc/conf.py

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
# sys.path.insert(0, os.path.abspath('.'))
1616

1717
import datetime
18+
from docutils import nodes
1819

1920
# -- Project information -----------------------------------------------------
2021

@@ -51,11 +52,11 @@
5152
suppress_warnings = [ 'misc.highlighting_failure' ]
5253

5354
def on_missing_reference(app, env, node, contnode):
54-
if node['reftype'] == 'any':
55-
contnode['refuri'] = "https://github.com/intel/llvm/tree/sycl/sycl/doc/" + node['reftarget']
56-
return contnode
57-
else:
58-
return None
55+
new_target = "https://github.com/intel/llvm/tree/sycl/sycl/doc/" + node['reftarget']
56+
57+
newnode = nodes.reference('', '', internal=False, refuri=new_target)
58+
newnode.append(contnode)
59+
return newnode
5960

6061
def setup(app):
6162
app.connect('missing-reference', on_missing_reference)

‎sycl/include/CL/sycl/accessor.hpp

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1560,12 +1560,17 @@ class accessor :
15601560
}
15611561

15621562
template <int Dims = Dimensions>
1563-
operator typename detail::enable_if_t<
1564-
Dims == 0 && AccessMode == access::mode::atomic, atomic<DataT, AS>>()
1565-
const {
1566-
const size_t LinearIndex = getLinearIndex(id<AdjustedDim>());
1567-
return atomic<DataT, AS>(
1568-
multi_ptr<DataT, AS>(getQualifiedPtr() + LinearIndex));
1563+
operator typename detail::enable_if_t<Dims == 0 &&
1564+
#ifdef __ENABLE_USM_ADDR_SPACE__
1565+
AccessMode == access::mode::atomic,
1566+
atomic<DataT>>() const {
1567+
#else
1568+
AccessMode == access::mode::atomic,
1569+
atomic<DataT, AS>>() const {
1570+
#endif
1571+
const size_t LinearIndex = getLinearIndex(id<AdjustedDim>());
1572+
return atomic<DataT, AS>(
1573+
multi_ptr<DataT, AS>(getQualifiedPtr() + LinearIndex));
15691574
}
15701575

15711576
template <int Dims = Dimensions>

‎sycl/include/CL/sycl/stream.hpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -958,6 +958,16 @@ class __SYCL_EXPORT stream {
958958
const h_item<Dimensions> &RHS);
959959
};
960960

961+
#if __cplusplus >= 201703L
962+
// Byte (has to be converted to a numeric value)
963+
template <typename T>
964+
inline std::enable_if_t<std::is_same<T, std::byte>::value, const stream &>
965+
operator<<(const stream &, const T &) {
966+
static_assert(std::is_integral<T>(),
967+
"Convert the byte to a numeric value using std::to_integer");
968+
}
969+
#endif // __cplusplus >= 201703L
970+
961971
// Character
962972
inline const stream &operator<<(const stream &Out, const char C) {
963973
detail::write(Out.GlobalFlushBuf, Out.FlushBufferSize, Out.WIOffset, &C, 1);

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