DPC++ daily 2022-05-10

[SYCL][L0] Correctly use global timestamps, instead of context (#6122)

Signed-off-by: Jaime Arteaga <[email protected]>

DPC++ daily 2022-05-09

[SYCL] Add half non-assign math operators (#6061)

This PR adds missing half operations +-*/.

There are existing operations for the legacy class host_half_impl, however these were not extended to the half class. These operations were being performed as floating point operations via the implicit floating conversion. This results in the output being a float not half type.

The template is limited to arithmetic types to prevent ambiguous templating.
A minor change to built-in __fract is needed to ensure fmin is not ambiguous.

llvm-test-suite PR: intel/llvm-test-suite#1012
Fixes: #6028

DPC++ daily 2022-05-07

[ESIMD] Bump up vc-intrinsics repo commit hash. (#6116)

The new commit has necessary fixes to support slm_init with non-constant (Specialization constant) argument.
Signed-off-by: Konstantin S Bobrovsky [email protected]

DPC++ daily 2022-05-06

sycl-nightly/20220506

[SYCL] Cast some unused variable as void in bfloat16.hpp (#6111)

DPC++ daily 2022-05-05

[SYCL] Fix properties include dependency in fpga extensions (#6101)

* [SYCL] Fix include dependency in fpga_lsu.hpp and pipes.hpp

fpga_lsu.hpp/pipes.hpp uses the compile-time properties extension but does not
include the corresponding header file. This issue only shows up when
the fpga extension header (or fpga_lsu.hpp directly) is included before
sycl.hpp. These changes resolve the include dependency.

Signed-off-by: Larsen, Steffen <[email protected]>

DPC++ daily 2022-05-04

[SYCL] Guard access to the cache of device lib programs (#6094)

We cache device library programs (like fallback assertion) in the
context. In multi-threaded applications simultaneous access to the
cache of device lib programs is possible in program_manager::build().
That's why access to the this cache needs to be guarded to avoid data
race.

DPC++ daily 2022-05-03

[SYCL][CUDA] Ignore cuda prefetch hint if not supported (#5043)

Specific devices and OS's, like Windows, do not support concurrent managed memory. cudaPrefetchAsync requires concurrent managed access for unified memory. This PR removes the windows error message and replaces it with a check for concurrent managed access. As the SYCL prefetch operation is a hint, this can return a success.

Let me know if there is a preferred error code to throw. Also, if it is best that a user warning is printed to indicate that the hint is being ignored as the device does not support the operation.

DPC++ daily 2022-05-02

LLVM and SPIRV-LLVM-Translator pulldown (WW18)

LLVM: https://github.com/llvm/llvm-project/commit/483efc9ad04dccd9f2163c84c2b6198ebb7049a6
SPIRV-LLVM-Translator: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/28fdb7ace62ac33af43374f8e52f6479073ae594

DPC++ daily 2022-05-01

LLVM and SPIRV-LLVM-Translator pulldown (WW18)

LLVM: https://github.com/llvm/llvm-project/commit/483efc9ad04dccd9f2163c84c2b6198ebb7049a6
SPIRV-LLVM-Translator: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/28fdb7ace62ac33af43374f8e52f6479073ae594

DPC++ daily 2022-04-30

LLVM and SPIRV-LLVM-Translator pulldown (WW18)

LLVM: https://github.com/llvm/llvm-project/commit/483efc9ad04dccd9f2163c84c2b6198ebb7049a6
SPIRV-LLVM-Translator: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/28fdb7ace62ac33af43374f8e52f6479073ae594