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Add intrinsics for bindless buffers support
write_predef_surface is main intrinsic to initialize %bss. Other intrinsics are duplicates of original intrinsics with ability to work with %bss variable.
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‎GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py

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"jump_table" : { "result" : "anyptr",
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"arguments" : ["anyint", "vararg"],
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"attributes" : "NoMem"
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}
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},
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## ``llvm.genx.write.predef.surface`` : write predefined surface variable
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * arg0: ptr predefined surface variable
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## * arg1: i32 value to write
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##
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## This corresponds to MOVS visa instruction and utilizes technique of using
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## global variable in LLVM IR for predefined surfaces.
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##
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"write_predef_surface" : { "result": "void",
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"arguments" : ["anyptr", "int"],
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"attributes" : "WriteMem",
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},
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## Internal VC memory intrinsics.
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## These versions are supposed to use predefined visa variables like %bss.
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## Intrinsics are supposed to be internal to VC backend.
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## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with binary operator with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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## * ``llvm.genx.dword.atomic2.add.predef.surface`` : vISA DWORD_ATOMIC ADD instruction
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## * ``llvm.genx.dword.atomic2.sub.predef.surface`` : vISA DWORD_ATOMIC SUB instruction
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## * ``llvm.genx.dword.atomic2.min.predef.surface`` : vISA DWORD_ATOMIC MIN instruction
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## * ``llvm.genx.dword.atomic2.max.predef.surface`` : vISA DWORD_ATOMIC MAX instruction
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## * ``llvm.genx.dword.atomic2.xchg.predef.surface`` : vISA DWORD_ATOMIC XCHG instruction
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## * ``llvm.genx.dword.atomic2.and.predef.surface`` : vISA DWORD_ATOMIC AND instruction
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## * ``llvm.genx.dword.atomic2.or.predef.surface`` : vISA DWORD_ATOMIC OR instruction
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## * ``llvm.genx.dword.atomic2.xor.predef.surface`` : vISA DWORD_ATOMIC XOR instruction
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## * ``llvm.genx.dword.atomic2.imin.predef.surface`` : vISA DWORD_ATOMIC IMIN instruction
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## * ``llvm.genx.dword.atomic2.imax.predef.surface`` : vISA DWORD_ATOMIC IMAX instruction
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: ptr predefined surface (overloaded)
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## * arg2: vXi32 element offset in bytes (overloaded)
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## * arg3: vXi32 src
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##
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## * Return value: vXi32 the old value read
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##
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## Predicate, element offset, src, and the return value must all have the
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## same vector width, which must be 1, 8 or 16.
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##
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"dword_atomic2_add_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_sub_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_min_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_max_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_xchg_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_and_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_or_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_xor_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_imin_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_imax_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with fmin/fmax operation with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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## * ``llvm.genx.dword.atomic2.fmin.predef.surface`` : vISA DWORD_ATOMIC FMIN instruction
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## * ``llvm.genx.dword.atomic2.fmax.predef.surface`` : vISA DWORD_ATOMIC FMAX instruction
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: ptr predefined surface (overloaded)
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## * arg2: vXi32 element offset in bytes (overloaded)
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## * arg3: vXfloat src
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##
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## * Return value: vXfloat the old value read
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##
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## Predicate, element offset, src, and the return value must all have the
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## same vector width, which must be 1, 8 or 16.
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##
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"dword_atomic2_fmin_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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"dword_atomic2_fmax_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0],
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"attributes" : "None",
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},
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## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec operation with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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## * ``llvm.genx.dword.atomic2.inc.predef.surface`` : vISA DWORD_ATOMIC INC instruction
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## * ``llvm.genx.dword.atomic2.dec.predef.surface`` : vISA DWORD_ATOMIC DEC instruction
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: ptr predefined surface (overloaded)
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## * arg2: vXi32 element offset in bytes (overloaded)
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##
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## * Return value: vXi32 the old value read
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##
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## Predicate, element offset, src, and the return value must all have the
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## same vector width, which must be 1, 8 or 16.
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##
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"dword_atomic2_inc_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint"],
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"attributes" : "None",
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},
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"dword_atomic2_dec_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint"],
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"attributes" : "None",
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},
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## ``llvm.genx.dword.atomic2.cmpxchg.predef.surface`` : vISA DWORD_ATOMIC CMPXCHG instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: ptr predefined surface (overloaded)
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## * arg2: vXi32 element offset in bytes (overloaded)
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## * arg3: vXi32 src0
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## * arg4: vXi32 src1
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##
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## * Return value: vXi32 the old value read
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##
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## Predicate, element offset, src, and the return value must all have the
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## same vector width, which must be 1, 8 or 16.
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##
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"dword_atomic2_cmpxchg_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0,0],
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"attributes" : "None",
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},
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## ``llvm.genx.dword.atomic2.fcmpwr.predef.surface`` : vISA DWORD_ATOMIC FCMPWR instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: ptr predefined surface (overloaded)
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## * arg2: vXi32 element offset in bytes (overloaded)
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## * arg3: vXfloat src0
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## * arg4: vXfloat src1
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##
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## * Return value: vXfloat the old value read
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##
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## Predicate, element offset, src, and the return value must all have the
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## same vector width, which must be 1, 8 or 16.
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##
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"dword_atomic2_fcmpwr_predef_surface" : { "result" : "anyvector",
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"arguments" : ["anyvector","anyptr","anyint",0,0],
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"attributes" : "None",
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},
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## ``llvm.genx.gather.masked.scaled2.predef.surface`` : vISA GATHER_SCALED instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4)
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## * arg1: i16 scale, constant
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## * arg2: ptr predefined surface (overloaded)
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## * arg3: i32 global offset in bytes
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## * arg4: vXi32 element offset in bytes (overloaded)
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## * arg5: vXi1 predicate (overloaded)
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##
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## * Return value: vXi32/float the data read
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##
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"gather_masked_scaled2_predef_surface" : { "result" : "anyvector",
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"arguments" : ["int","short","anyptr","int","anyint","anyvector"],
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"attributes" : "ReadMem",
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},
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## ``llvm.genx.gather4.masked.scaled2.predef.surface`` : vISA GATHER4_SCALED instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: i32 channel mask, constant
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## * arg1: i16 scale, constant
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## * arg2: ptr predefined surface (overloaded)
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## * arg3: i32 global offset in bytes
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## * arg4: vXi32 element offset in bytes
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## * arg5: vXi1 predicate (overloaded)
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##
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## * Return value: vXi32/float the data read
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##
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"gather4_masked_scaled2_predef_surface" : { "result" : "anyvector",
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"arguments" : ["int","short","anyptr","int","anyint","anyvector"],
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"attributes" : "ReadMem",
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},
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## ``llvm.genx.scatter.scaled.predef.surface`` : vISA SCATTER_SCALED instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: i32 log2 num blocks, constant (0/1/2 for num blocks 1/2/4)
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## * arg2: i16 scale, constant
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## * arg3: ptr predefined surface (overloaded)
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## * arg4: i32 global offset in bytes
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## * arg5: vXi32 element offset (overloaded)
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## * arg6: data to write (overloaded)
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##
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## The vector width of the element offset arg is the number of elements to
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## write, which must be power of 2 and less than or equal to 32.
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##
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## The predicate arg must have the same vector width.
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##
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## The data type to write must have UD, D or F type. For 1 and 2 byte (1 x num
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## blocks) accesses the upper bytes will be ignored.
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##
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"scatter_scaled_predef_surface" : { "result" : "void",
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"arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"],
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"attributes" : "None",
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},
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## ``llvm.genx.scatter4.scaled.predef.surface`` : vISA SCATTER4_SCALED instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (Exec_size inferred from element offset type)
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## * arg0: vXi1 predicate (overloaded)
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## * arg1: i32 channel mask, constant
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## * arg2: i16 scale, constant
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## * arg3: ptr predefined surface (overloaded)
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## * arg4: i32 global offset in bytes
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## * arg5: vXi32 element offset in bytes (overloaded)
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## * arg6: data to write (overloaded)
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##
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## The vector width of the element offset arg is the number of elements to
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## write, which must be 8 or 16.
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## The predicate arg must have the same vector width.
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## The instruction writes up to 4 channels per element, with the lowest 4
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## bits of the channel mask arg giving the mask of channels _not_ to read.
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## The number of 0 bits in that lower 4 bits of the channel mask arg is the
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## number of channels to write per element.
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## The channels to write must be contiguous and starting at channel 0.
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## The vector width of the data to write must be the number of elements
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## times the number of channels to write per element.
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## The element type of the data to write must be i32 or float.
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##
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"scatter4_scaled_predef_surface" : { "result" : "void",
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"arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"],
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"attributes" : "None",
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},
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## ``llvm.genx.oword.ld*.predef.surface`` : oword load instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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## * ``llvm.genx.oword.ld.predef.surface`` : vISA OWORD_LD instruction
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## * ``llvm.genx.oword.ld.unaligned.predef.surface`` : vISA OWORD_LD_UNALIGNED instruction
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##
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## * (log2 number of owords inferred from return type)
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## * arg0: i32 is_modified, constant
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## * arg1: ptr predefined surface variable (overloaded)
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## * arg2: i32 offset (in owords for .ld / in bytes for .ld.unaligned)
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##
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## * Return value: vXiN the data read.
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##
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## The byte size of the return type must be 16, 32, 64, or 128.
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##
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"oword_ld_predef_surface" : { "result" : "anyvector",
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"arguments" : ["int", "anyptr", "int"],
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"attributes": "ReadMem",
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},
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"oword_ld_unaligned_predef_surface" : { "result" : "anyvector",
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"arguments": ["int", "anyptr", "int"],
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"attributes" : "ReadMem",
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},
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## ``llvm.genx.oword.st.predef.surface`` : vISA OWORD_ST instruction with predefined surface
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## ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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##
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## * (log2 number of owords inferred from return type)
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## * arg0: ptr predefined surface variable (overloaded)
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## * arg1: i32 offset (in owords)
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## * arg2: data to write (overloaded)
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##
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## The byte size of the data to write must be 16, 32, 64, or 128.
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##
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"oword_st_predef_surface" : { "result" : "void",
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"arguments" : ["anyptr", "int", "anyvector"],
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"attributes" : "None",
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},
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}

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