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MaheshRavishankarMaheshRavishankar
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Revert "Revert "[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (llvm#119461)""
This reverts commit 0f42dbd.
1 parent 0bdbc1c commit 40367f2

35 files changed

+143
-230
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
105105
static cl::opt<bool>
106106
EnableVLOptimizer("riscv-enable-vl-optimizer",
107107
cl::desc("Enable the RISC-V VL Optimizer pass"),
108-
cl::init(false), cl::Hidden);
108+
cl::init(true), cl::Hidden);
109109

110110
static cl::opt<bool> DisableVectorMaskMutation(
111111
"riscv-disable-vector-mask-mutation",

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@
119119
; RV64-NEXT: RISC-V Optimize W Instructions
120120
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
121121
; CHECK-NEXT: RISC-V Merge Base Offset
122+
; CHECK-NEXT: MachineDominator Tree Construction
123+
; CHECK-NEXT: RISC-V VL Optimizer
122124
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
123125
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
124126
; CHECK-NEXT: RISC-V Landing Pad Setup
@@ -129,7 +131,6 @@
129131
; CHECK-NEXT: Live Variable Analysis
130132
; CHECK-NEXT: Eliminate PHI nodes for register allocation
131133
; CHECK-NEXT: Two-Address instruction pass
132-
; CHECK-NEXT: MachineDominator Tree Construction
133134
; CHECK-NEXT: Slot index numbering
134135
; CHECK-NEXT: Live Interval Analysis
135136
; CHECK-NEXT: Register Coalescer

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2654,9 +2654,8 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26542654
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
26552655
; CHECK: # %bb.0:
26562656
; CHECK-NEXT: li a1, 511
2657-
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2658-
; CHECK-NEXT: vxor.vx v8, v8, a1
26592657
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2658+
; CHECK-NEXT: vxor.vx v8, v8, a1
26602659
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
26612660
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
26622661
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -2670,9 +2669,8 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26702669
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
26712670
; CHECK-ZVBB: # %bb.0:
26722671
; CHECK-ZVBB-NEXT: li a1, 511
2673-
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2674-
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
26752672
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2673+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
26762674
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
26772675
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26782676
; CHECK-ZVBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,7 @@ define void @abs_v6i16(ptr %x) {
3939
; CHECK: # %bb.0:
4040
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4141
; CHECK-NEXT: vle16.v v8, (a0)
42-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4342
; CHECK-NEXT: vrsub.vi v9, v8, 0
44-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4543
; CHECK-NEXT: vmax.vv v8, v8, v9
4644
; CHECK-NEXT: vse16.v v8, (a0)
4745
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -780,11 +780,9 @@ define void @copysign_v6bf16(ptr %x, ptr %y) {
780780
; CHECK-NEXT: vle16.v v8, (a1)
781781
; CHECK-NEXT: vle16.v v9, (a0)
782782
; CHECK-NEXT: lui a1, 8
783-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
784783
; CHECK-NEXT: vand.vx v8, v8, a1
785784
; CHECK-NEXT: addi a1, a1, -1
786785
; CHECK-NEXT: vand.vx v9, v9, a1
787-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
788786
; CHECK-NEXT: vor.vv v8, v9, v8
789787
; CHECK-NEXT: vse16.v v8, (a0)
790788
; CHECK-NEXT: ret
@@ -840,11 +838,9 @@ define void @copysign_v6f16(ptr %x, ptr %y) {
840838
; ZVFHMIN-NEXT: vle16.v v8, (a1)
841839
; ZVFHMIN-NEXT: vle16.v v9, (a0)
842840
; ZVFHMIN-NEXT: lui a1, 8
843-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
844841
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
845842
; ZVFHMIN-NEXT: addi a1, a1, -1
846843
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
847-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
848844
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
849845
; ZVFHMIN-NEXT: vse16.v v8, (a0)
850846
; ZVFHMIN-NEXT: ret
@@ -916,12 +912,10 @@ define void @copysign_vf_v6bf16(ptr %x, bfloat %y) {
916912
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
917913
; CHECK-NEXT: vle16.v v8, (a0)
918914
; CHECK-NEXT: lui a2, 8
919-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
920915
; CHECK-NEXT: vmv.v.x v9, a1
921916
; CHECK-NEXT: addi a1, a2, -1
922917
; CHECK-NEXT: vand.vx v8, v8, a1
923918
; CHECK-NEXT: vand.vx v9, v9, a2
924-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
925919
; CHECK-NEXT: vor.vv v8, v8, v9
926920
; CHECK-NEXT: vse16.v v8, (a0)
927921
; CHECK-NEXT: ret
@@ -978,12 +972,10 @@ define void @copysign_vf_v6f16(ptr %x, half %y) {
978972
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
979973
; ZVFHMIN-NEXT: vle16.v v8, (a0)
980974
; ZVFHMIN-NEXT: lui a2, 8
981-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
982975
; ZVFHMIN-NEXT: vmv.v.x v9, a1
983976
; ZVFHMIN-NEXT: addi a1, a2, -1
984977
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
985978
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
986-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
987979
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
988980
; ZVFHMIN-NEXT: vse16.v v8, (a0)
989981
; ZVFHMIN-NEXT: ret
@@ -1057,11 +1049,9 @@ define void @copysign_neg_v6bf16(ptr %x, ptr %y) {
10571049
; CHECK-NEXT: vle16.v v9, (a0)
10581050
; CHECK-NEXT: lui a1, 8
10591051
; CHECK-NEXT: addi a2, a1, -1
1060-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
10611052
; CHECK-NEXT: vxor.vx v8, v8, a1
10621053
; CHECK-NEXT: vand.vx v9, v9, a2
10631054
; CHECK-NEXT: vand.vx v8, v8, a1
1064-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
10651055
; CHECK-NEXT: vor.vv v8, v9, v8
10661056
; CHECK-NEXT: vse16.v v8, (a0)
10671057
; CHECK-NEXT: ret
@@ -1121,11 +1111,9 @@ define void @copysign_neg_v6f16(ptr %x, ptr %y) {
11211111
; ZVFHMIN-NEXT: vle16.v v9, (a0)
11221112
; ZVFHMIN-NEXT: lui a1, 8
11231113
; ZVFHMIN-NEXT: addi a2, a1, -1
1124-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11251114
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
11261115
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
11271116
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
1128-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
11291117
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
11301118
; ZVFHMIN-NEXT: vse16.v v8, (a0)
11311119
; ZVFHMIN-NEXT: ret
@@ -1207,7 +1195,6 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
12071195
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
12081196
; CHECK-NEXT: vxor.vx v9, v10, a1
12091197
; CHECK-NEXT: vand.vx v9, v9, a1
1210-
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12111198
; CHECK-NEXT: vor.vv v8, v8, v9
12121199
; CHECK-NEXT: vse16.v v8, (a0)
12131200
; CHECK-NEXT: ret
@@ -1272,12 +1259,10 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
12721259
; ZVFHMIN-NEXT: vle32.v v9, (a1)
12731260
; ZVFHMIN-NEXT: lui a1, 8
12741261
; ZVFHMIN-NEXT: addi a2, a1, -1
1275-
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12761262
; ZVFHMIN-NEXT: vand.vx v8, v8, a2
12771263
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
12781264
; ZVFHMIN-NEXT: vxor.vx v9, v10, a1
12791265
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
1280-
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12811266
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
12821267
; ZVFHMIN-NEXT: vse16.v v8, (a0)
12831268
; ZVFHMIN-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -909,8 +909,9 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
909909
define <16 x i8> @buildvec_not_vid_v16i8() {
910910
; CHECK-LABEL: buildvec_not_vid_v16i8:
911911
; CHECK: # %bb.0:
912-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
912+
; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma
913913
; CHECK-NEXT: vmv.v.i v9, 3
914+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
914915
; CHECK-NEXT: vmv.v.i v8, 0
915916
; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma
916917
; CHECK-NEXT: vslideup.vi v8, v9, 6

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -348,8 +348,9 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
348348
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
349349
; CHECK-LABEL: splat_ve4_ins_i1ve3:
350350
; CHECK: # %bb.0:
351-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
351+
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, ma
352352
; CHECK-NEXT: vmv.v.i v9, 3
353+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
353354
; CHECK-NEXT: vmv.v.i v10, 4
354355
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
355356
; CHECK-NEXT: vslideup.vi v10, v9, 1
@@ -432,8 +433,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
432433
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
433434
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
434435
; CHECK: # %bb.0:
435-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
436+
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, ma
436437
; CHECK-NEXT: vmv.v.i v10, 4
438+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
437439
; CHECK-NEXT: vmv.v.i v11, 0
438440
; CHECK-NEXT: li a0, 70
439441
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1100,15 +1100,17 @@ define void @mulhu_v8i16(ptr %x) {
11001100
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11011101
; CHECK-NEXT: vle16.v v8, (a0)
11021102
; CHECK-NEXT: vmv.v.i v9, 0
1103+
; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
11031104
; CHECK-NEXT: vmv.v.i v10, 1
11041105
; CHECK-NEXT: li a1, 33
11051106
; CHECK-NEXT: vmv.s.x v0, a1
11061107
; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
11071108
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
1109+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11081110
; CHECK-NEXT: vmv.v.i v11, 3
11091111
; CHECK-NEXT: vle16.v v12, (a1)
11101112
; CHECK-NEXT: vmerge.vim v11, v11, 2, v0
1111-
; CHECK-NEXT: vmv.v.i v13, 0
1113+
; CHECK-NEXT: vmv1r.v v13, v9
11121114
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
11131115
; CHECK-NEXT: vslideup.vi v9, v10, 6
11141116
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,8 +97,9 @@ define <4 x i32> @v4i32_v8i32(<8 x i32>) {
9797
define <4 x i32> @v4i32_v16i32(<16 x i32>) {
9898
; RV32-LABEL: v4i32_v16i32:
9999
; RV32: # %bb.0:
100-
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
100+
; RV32-NEXT: vsetivli zero, 2, e16, m1, ta, ma
101101
; RV32-NEXT: vmv.v.i v12, 1
102+
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
102103
; RV32-NEXT: vmv.v.i v14, 6
103104
; RV32-NEXT: li a0, 32
104105
; RV32-NEXT: vmv.v.i v0, 10

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