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[WebAssembly] Refactor PerformSETCCCombine (llvm#144875)
Extract the logic into a templated helper function.
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1 file changed

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llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

Lines changed: 59 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -3239,52 +3239,79 @@ static SDValue performBitcastCombine(SDNode *N,
32393239
return SDValue();
32403240
}
32413241

3242-
static SDValue performSETCCCombine(SDNode *N,
3243-
TargetLowering::DAGCombinerInfo &DCI) {
3244-
auto &DAG = DCI.DAG;
3245-
3242+
template <int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate,
3243+
Intrinsic::ID Intrin>
3244+
static SDValue TryMatchTrue(SDNode *N, EVT VecVT, SelectionDAG &DAG) {
32463245
SDValue LHS = N->getOperand(0);
32473246
SDValue RHS = N->getOperand(1);
3248-
ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
3247+
SDValue Cond = N->getOperand(2);
3248+
if (MatchCond != cast<CondCodeSDNode>(Cond)->get())
3249+
return SDValue();
3250+
3251+
if (MatchRHS != cast<ConstantSDNode>(RHS)->getSExtValue())
3252+
return SDValue();
3253+
32493254
SDLoc DL(N);
3255+
SDValue Ret = DAG.getZExtOrTrunc(
3256+
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3257+
{DAG.getConstant(Intrin, DL, MVT::i32),
3258+
DAG.getSExtOrTrunc(LHS->getOperand(0), DL, VecVT)}),
3259+
DL, MVT::i1);
3260+
if (RequiresNegate)
3261+
Ret = DAG.getNOT(DL, Ret, MVT::i1);
3262+
return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
3263+
}
3264+
3265+
static SDValue performSETCCCombine(SDNode *N,
3266+
TargetLowering::DAGCombinerInfo &DCI) {
3267+
if (!DCI.isBeforeLegalize())
3268+
return SDValue();
3269+
32503270
EVT VT = N->getValueType(0);
3271+
if (!VT.isScalarInteger())
3272+
return SDValue();
32513273

3274+
SDValue LHS = N->getOperand(0);
3275+
if (LHS->getOpcode() != ISD::BITCAST)
3276+
return SDValue();
3277+
3278+
EVT FromVT = LHS->getOperand(0).getValueType();
3279+
if (!FromVT.isFixedLengthVector() || FromVT.getVectorElementType() != MVT::i1)
3280+
return SDValue();
3281+
3282+
unsigned NumElts = FromVT.getVectorNumElements();
3283+
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3284+
return SDValue();
3285+
3286+
if (!cast<ConstantSDNode>(N->getOperand(1)))
3287+
return SDValue();
3288+
3289+
EVT VecVT = FromVT.changeVectorElementType(MVT::getIntegerVT(128 / NumElts));
3290+
auto &DAG = DCI.DAG;
32523291
// setcc (iN (bitcast (vNi1 X))), 0, ne
32533292
// ==> any_true (vNi1 X)
3293+
if (auto Match = TryMatchTrue<0, ISD::SETNE, false, Intrinsic::wasm_anytrue>(
3294+
N, VecVT, DAG)) {
3295+
return Match;
3296+
}
32543297
// setcc (iN (bitcast (vNi1 X))), 0, eq
32553298
// ==> xor (any_true (vNi1 X)), -1
3299+
if (auto Match = TryMatchTrue<0, ISD::SETEQ, true, Intrinsic::wasm_anytrue>(
3300+
N, VecVT, DAG)) {
3301+
return Match;
3302+
}
32563303
// setcc (iN (bitcast (vNi1 X))), -1, eq
32573304
// ==> all_true (vNi1 X)
3305+
if (auto Match = TryMatchTrue<-1, ISD::SETEQ, false, Intrinsic::wasm_alltrue>(
3306+
N, VecVT, DAG)) {
3307+
return Match;
3308+
}
32583309
// setcc (iN (bitcast (vNi1 X))), -1, ne
32593310
// ==> xor (all_true (vNi1 X)), -1
3260-
if (DCI.isBeforeLegalize() && VT.isScalarInteger() &&
3261-
(Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3262-
(isNullConstant(RHS) || isAllOnesConstant(RHS)) &&
3263-
LHS->getOpcode() == ISD::BITCAST) {
3264-
EVT FromVT = LHS->getOperand(0).getValueType();
3265-
if (FromVT.isFixedLengthVector() &&
3266-
FromVT.getVectorElementType() == MVT::i1) {
3267-
int Intrin = isNullConstant(RHS) ? Intrinsic::wasm_anytrue
3268-
: Intrinsic::wasm_alltrue;
3269-
unsigned NumElts = FromVT.getVectorNumElements();
3270-
if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3271-
return SDValue();
3272-
EVT Width = MVT::getIntegerVT(128 / NumElts);
3273-
SDValue Ret = DAG.getZExtOrTrunc(
3274-
DAG.getNode(
3275-
ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3276-
{DAG.getConstant(Intrin, DL, MVT::i32),
3277-
DAG.getSExtOrTrunc(LHS->getOperand(0), DL,
3278-
FromVT.changeVectorElementType(Width))}),
3279-
DL, MVT::i1);
3280-
if ((isNullConstant(RHS) && (Cond == ISD::SETEQ)) ||
3281-
(isAllOnesConstant(RHS) && (Cond == ISD::SETNE))) {
3282-
Ret = DAG.getNOT(DL, Ret, MVT::i1);
3283-
}
3284-
return DAG.getZExtOrTrunc(Ret, DL, VT);
3285-
}
3311+
if (auto Match = TryMatchTrue<-1, ISD::SETNE, true, Intrinsic::wasm_alltrue>(
3312+
N, VecVT, DAG)) {
3313+
return Match;
32863314
}
3287-
32883315
return SDValue();
32893316
}
32903317

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