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[AMDGPU] Disallow null for more resource operands
Following on from llvm#115200, disallow the null sgpr as a resource operand in some instructions that were missed.
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9 files changed

+52
-12
lines changed

9 files changed

+52
-12
lines changed

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ multiclass MUBUF_Pseudo_Stores<string opName, ValueType store_vt = i32> {
680680
class MUBUF_Pseudo_Store_Lds<string opName>
681681
: MUBUF_Pseudo<opName,
682682
(outs),
683-
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
683+
(ins SReg_128_XNULL:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
684684
" $srsrc, $soffset$offset lds$cpol"> {
685685
let LGKM_CNT = 1;
686686
let mayLoad = 1;

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1524,21 +1524,21 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16> {
15241524

15251525
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
15261526
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
1527-
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
1527+
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
15281528
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
15291529

15301530
let nsa = 0;
15311531
}
15321532

15331533
class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
15341534
: MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "GFX10"> {
1535-
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
1535+
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$srsrc, A16:$a16));
15361536
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
15371537
}
15381538

15391539
class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
15401540
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
1541-
let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
1541+
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
15421542
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
15431543

15441544
let nsa = 0;
@@ -1548,15 +1548,15 @@ class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
15481548
list<RegisterClass> addr_types>
15491549
: MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "GFX11",
15501550
addr_types> {
1551-
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
1551+
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$srsrc, A16:$a16));
15521552
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
15531553
}
15541554

15551555
class VIMAGE_IntersectRay_gfx12<mimgopc op, string opcode, int num_addrs,
15561556
list<RegisterClass> addr_types>
15571557
: VIMAGE_gfx12<op.GFX12, (outs VReg_128:$vdata),
15581558
num_addrs, "GFX12", addr_types> {
1559-
let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$rsrc, A16:$a16));
1559+
let InOperandList = !con(nsah.AddrIns, (ins SReg_128_XNULL:$rsrc, A16:$a16));
15601560
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $rsrc$a16";
15611561
}
15621562

‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -341,10 +341,10 @@ let SubtargetPredicate = HasScalarDwordx3Loads in
341341
defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_128>;
342342
defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_256>;
343343
defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_512>;
344-
defm S_BUFFER_LOAD_I8 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
345-
defm S_BUFFER_LOAD_U8 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
346-
defm S_BUFFER_LOAD_I16 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
347-
defm S_BUFFER_LOAD_U16 : SM_Pseudo_Loads <SReg_128, SReg_32_XM0_XEXEC>;
344+
defm S_BUFFER_LOAD_I8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
345+
defm S_BUFFER_LOAD_U8 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
346+
defm S_BUFFER_LOAD_I16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
347+
defm S_BUFFER_LOAD_U16 : SM_Pseudo_Loads <SReg_128_XNULL, SReg_32_XM0_XEXEC>;
348348
}
349349

350350
let SubtargetPredicate = HasScalarStores in {
@@ -375,7 +375,7 @@ def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb
375375

376376
defm S_ATC_PROBE : SM_Pseudo_Probe <SReg_64>;
377377
let is_buffer = 1 in {
378-
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <SReg_128>;
378+
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <SReg_128_XNULL>;
379379
}
380380
} // SubtargetPredicate = isGFX8Plus
381381

@@ -470,7 +470,7 @@ def S_PREFETCH_INST : SM_Prefetch_Pseudo <"s_prefetch_inst", SReg_64, 1>;
470470
def S_PREFETCH_INST_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_inst_pc_rel", SReg_64, 0>;
471471
def S_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_prefetch_data", SReg_64, 1>;
472472
def S_PREFETCH_DATA_PC_REL : SM_Prefetch_Pseudo <"s_prefetch_data_pc_rel", SReg_64, 0>;
473-
def S_BUFFER_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_buffer_prefetch_data", SReg_128, 1> {
473+
def S_BUFFER_PREFETCH_DATA : SM_Prefetch_Pseudo <"s_buffer_prefetch_data", SReg_128_XNULL, 1> {
474474
let is_buffer = 1;
475475
}
476476
} // end let SubtargetPredicate = isGFX12Plus

‎llvm/test/MC/AMDGPU/gfx1030_err.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -573,3 +573,9 @@ v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,0]
573573

574574
v_dot8_u32_u4 v0, v1, v2, v3 op_sel:[1,1] op_sel_hi:[1,1]
575575
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
576+
577+
image_bvh_intersect_ray v[4:7], v[9:19], null
578+
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
579+
580+
image_bvh64_intersect_ray v[4:7], v[9:20], null
581+
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx10_asm_smem_err.s

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,3 +84,5 @@ s_buffer_load_dwordx16 s[4:19], null, s101
8484
s_buffer_store_dword s4, null, s101
8585
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8686

87+
s_atc_probe_buffer 7, null, s2
88+
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -517,3 +517,9 @@ image_sample_o v[5:6], v[1:2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
517517

518518
image_sample_o v[5:6], v[1:2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
519519
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
520+
521+
image_bvh_intersect_ray v[4:7], v[9:19], null
522+
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
523+
524+
image_bvh64_intersect_ray v[4:7], v[9:20], null
525+
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx11_asm_smem_err.s

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,6 @@ s_buffer_load_dwordx8 s[4:11], null, s101
2929

3030
s_buffer_load_dwordx16 s[4:19], null, s101
3131
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
32+
33+
s_atc_probe_buffer 7, null, s2
34+
// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx12_asm_mimg_err.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -374,3 +374,8 @@ image_sample_o v[5:6], [v1, v2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
374374
image_sample_o v[5:6], [v1, v2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
375375
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
376376

377+
image_bvh_intersect_ray v[4:7], [v9, v10, v[11:13], v[14:16], v[17:19]], null
378+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
379+
380+
image_bvh64_intersect_ray v[4:7], [v[9:10], v11, v[12:14], v[15:17], v[18:20]], null
381+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx12_asm_smem_err.s

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,21 @@ s_buffer_load_dwordx8 s[4:11], null, s101
2929

3030
s_buffer_load_dwordx16 s[4:19], null, s101
3131
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
32+
33+
s_atc_probe_buffer 7, null, s2
34+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
35+
36+
s_buffer_prefetch_data null, 100, s10, 7
37+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
38+
39+
s_buffer_load_i8 s5, null, s0
40+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
41+
42+
s_buffer_load_u8 s5, null, s0
43+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
44+
45+
s_buffer_load_i16 s5, null, s0
46+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
47+
48+
s_buffer_load_u16 s5, null, s0
49+
// NOGFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

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