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[RISCV] Add Xqccmp 0.1 Assembly Support (llvm#128731)
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp instructions and reverse the order they push/pop registers in, which ends up matching the frame pointer convention. This extension adds a new instruction not present in Zcmp, `qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it has pushed the registers. This change duplicates the Zcmp implementation, with minor changes to mnemonics (for the `qc.` prefix), predicates, and the addition of `qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the specs are separate today. Specification: https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
1 parent fb5b3d3 commit d23bb42

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lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -193,6 +193,7 @@
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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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// CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
196197
// CHECK-NEXT: xqcia 0.4 'Xqcia' (Qualcomm uC Arithmetic Extension)
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// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
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// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)

‎llvm/docs/RISCVUsage.rst

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@@ -429,6 +429,9 @@ The current vendor extensions supported are:
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``Xwchc``
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LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
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``experimental-Xqccmp``
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LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.
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``experimental-Xqcia``
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LLVM implements `version 0.4 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md

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@@ -109,6 +109,8 @@ Changes to the RISC-V Backend
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
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extension.
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* Adds experimental assembler support for the Qualcomm 'Xqccmp' extension, which
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is a frame-pointer convention compatible version of Zcmp.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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@@ -1682,6 +1682,17 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidRnumArg: {
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
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}
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case Match_InvalidStackAdj: {
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SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
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StringRef SpecName = "Zc";
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if (getSTI().hasFeature(RISCV::FeatureVendorXqccmp))
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SpecName = "Xqccmp";
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return Error(ErrorLoc,
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Twine("stack adjustment is invalid for this instruction") +
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" and register list; refer to " + SpecName +
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" spec for a detailed range of stack adjustment");
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}
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}
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16871698
if (const char *MatchDiag = getMatchKindDiag((RISCVMatchResultTy)Result)) {
@@ -3640,7 +3651,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
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}
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}
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3643-
if (Opcode == RISCV::CM_MVSA01) {
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if (Opcode == RISCV::CM_MVSA01 || Opcode == RISCV::QC_CM_MVSA01) {
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MCRegister Rd1 = Inst.getOperand(0).getReg();
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MCRegister Rd2 = Inst.getOperand(1).getReg();
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if (Rd1 == Rd2) {

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -748,7 +748,9 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
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TRY_TO_DECODE_FEATURE_ANY(XqciFeatureGroup, DecoderTableXqci16,
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"Qualcomm uC 16bit");
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TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXqccmp, DecoderTableXqccmp16,
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"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)");
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TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
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DecoderTableXwchc16, "WCH QingKe XW");
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TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1374,6 +1374,14 @@ def HasVendorXqcilo
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AssemblerPredicate<(all_of FeatureVendorXqcilo),
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"'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
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def FeatureVendorXqccmp
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: RISCVExperimentalExtension<0, 1,
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"Qualcomm 16-bit Push/Pop and Double Moves",
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[FeatureStdExtZca]>;
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def HasVendorXqccmp : Predicate<"Subtarget->hasVendorXqccmp()">,
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AssemblerPredicate<(all_of FeatureVendorXqccmp),
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"'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
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// Rivos Extension(s)
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def FeatureVendorXRivosVisni

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -2153,6 +2153,7 @@ include "RISCVInstrInfoSFB.td"
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include "RISCVInstrInfoXCV.td"
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include "RISCVInstrInfoXwch.td"
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include "RISCVInstrInfoXqci.td"
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include "RISCVInstrInfoXqccmp.td"
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include "RISCVInstrInfoXMips.td"
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include "RISCVInstrInfoXRivos.td"
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td

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@@ -0,0 +1,95 @@
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//===---------------- RISCVInstrInfoXqccmp.td --------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Qualcomm's Xqccmp extension.
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//
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// Xqccmp is broadly equivalent to (and incompatible with) Zcmp except the
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// following changes:
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//
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// - The registers are pushed in the opposite order, so `ra` and `fp` are
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// closest to the incoming stack pointer (to be compatible with the
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// frame-pointer convention), and
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//
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// - There is a new `qc.cm.pushfp` instruction which is `qc.cm.push` but it sets
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// `fp` to the incoming stack pointer value, as expected by the frame-pointer
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// convention.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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32+
//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
43+
let Defs = [X10, X11] in
44+
def QC_CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
45+
(ins SR07:$rs1, SR07:$rs2), "qc.cm.mva01s", "$rs1, $rs2">,
46+
Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
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48+
let Uses = [X10, X11] in
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def QC_CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
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(ins), "qc.cm.mvsa01", "$rs1, $rs2">,
51+
Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
52+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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54+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in
55+
def QC_CM_PUSH : RVInstZcCPPP<0b11000, "qc.cm.push", negstackadj>,
56+
Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
57+
ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
58+
ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
59+
ReadStoreData, ReadStoreData, ReadStoreData]>;
60+
61+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2, X8] in
62+
def QC_CM_PUSHFP : RVInstZcCPPP<0b11001, "qc.cm.pushfp", negstackadj>,
63+
Sched<[WriteIALU, WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
64+
ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
65+
ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
66+
ReadStoreData, ReadStoreData, ReadStoreData]>;
67+
68+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
69+
Uses = [X2], Defs = [X2] in
70+
def QC_CM_POPRET : RVInstZcCPPP<0b11110, "qc.cm.popret">,
71+
Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
72+
WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
73+
WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
74+
75+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
76+
Uses = [X2], Defs = [X2, X10] in
77+
def QC_CM_POPRETZ : RVInstZcCPPP<0b11100, "qc.cm.popretz">,
78+
Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,
79+
WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
80+
WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
81+
ReadIALU]>;
82+
83+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
84+
Uses = [X2], Defs = [X2] in
85+
def QC_CM_POP : RVInstZcCPPP<0b11010, "qc.cm.pop">,
86+
Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
87+
WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
88+
WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
89+
90+
} // DecoderNamespace = "Xqccmp", Predicates = [HasVendorXqccmp]
91+
92+
//===----------------------------------------------------------------------===//
93+
// Aliases
94+
//===----------------------------------------------------------------------===//
95+

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

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@@ -46,8 +46,6 @@ def StackAdjAsmOperand : AsmOperandClass {
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let Name = "StackAdj";
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let ParserMethod = "parseZcmpStackAdj";
4848
let DiagnosticType = "InvalidStackAdj";
49-
let DiagnosticString = "stack adjustment is invalid for this instruction and register list; "
50-
"refer to Zc spec for a detailed range of stack adjustment";
5149
let PredicateMethod = "isSpimm";
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let RenderMethod = "addSpimmOperands";
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}

‎llvm/lib/TargetParser/RISCVISAInfo.cpp

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@@ -745,6 +745,8 @@ Error RISCVISAInfo::checkDependency() {
745745
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
746746
{"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
747747
{"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
748+
bool HasZcmp = Exts.count("zcmp") != 0;
749+
bool HasXqccmp = Exts.count("xqccmp") != 0;
748750

749751
if (HasI && HasE)
750752
return getIncompatibleError("i", "e");
@@ -779,6 +781,9 @@ Error RISCVISAInfo::checkDependency() {
779781
if (Exts.count(Ext.str()) && (XLen != 32))
780782
return getError("'" + Twine(Ext) + "'" + " is only supported for 'rv32'");
781783

784+
if (HasZcmp && HasXqccmp)
785+
return getIncompatibleError("zcmp", "xqccmp");
786+
782787
return Error::success();
783788
}
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‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -81,6 +81,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV32XQCCMP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s
8586
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s
8687
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s
@@ -302,6 +303,8 @@
302303
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
303304
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
304305
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
306+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s
307+
305308

306309
; Tests for profile features.
307310
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
@@ -398,6 +401,7 @@
398401
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
399402
; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
400403
; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
404+
; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1"
401405
; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p4"
402406
; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"
403407
; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2"
@@ -617,6 +621,7 @@
617621
; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
618622
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
619623
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
624+
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p1"
620625

621626
; RVI20U32: .attribute 5, "rv32i2p1"
622627
; RVI20U64: .attribute 5, "rv64i2p1"

‎llvm/test/MC/RISCV/rv32xqccmp-invalid.s

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# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmp -M no-aliases -show-encoding < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
3+
4+
# CHECK-ERROR: error: invalid operand for instruction
5+
qc.cm.mvsa01 a1, a2
6+
7+
# CHECK-ERROR: error: rs1 and rs2 must be different
8+
qc.cm.mvsa01 s0, s0
9+
10+
# CHECK-ERROR: error: invalid operand for instruction
11+
qc.cm.mva01s a1, a2
12+
13+
# CHECK-ERROR: error: invalid register list, {ra, s0-s10} or {x1, x8-x9, x18-x26} is not supported
14+
qc.cm.popretz {ra, s0-s10}, 112
15+
16+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
17+
qc.cm.popretz {ra, s0-s1}, 112
18+
19+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
20+
qc.cm.push {ra}, 16
21+
22+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
23+
qc.cm.pushfp {ra, s0}, 16
24+
25+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
26+
qc.cm.pop {ra, s0-s1}, -32
27+
28+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
29+
qc.cm.push {ra}, -8
30+
31+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
32+
qc.cm.pushfp {ra, s0}, -12
33+
34+
# CHECK-ERROR: error: stack adjustment is invalid for this instruction and register list; refer to Xqccmp spec for a detailed range of stack adjustment
35+
qc.cm.pop {ra, s0-s1}, -40

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