With llvm#87539, previous commit that checks for the instruction immediately

after a load/store is not necessary.

Author: Jun Wang

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

@@ -2306,15 +2306,11 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
 #endif
 
     if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
-      ++Iter;
-      if (!isWaitInstr(*Iter)) {
-        AMDGPU::Waitcnt Wait = WCG->getAllZeroWaitcnt(
-            Inst.mayStore() && !SIInstrInfo::isAtomicRet(Inst));
-        ScoreBrackets.simplifyWaitcnt(Wait);
-        Modified |= generateWaitcnt(Wait, std::next(Inst.getIterator()), Block,
-                                    ScoreBrackets, /*OldWaitcntInstr=*/nullptr);
-      }
-      --Iter;
+      AMDGPU::Waitcnt Wait = WCG->getAllZeroWaitcnt(
+          Inst.mayStore() && !SIInstrInfo::isAtomicRet(Inst));
+      ScoreBrackets.simplifyWaitcnt(Wait);
+      Modified |= generateWaitcnt(Wait, std::next(Inst.getIterator()), Block,
+                                  ScoreBrackets, /*OldWaitcntInstr=*/nullptr);
     }
 
     LLVM_DEBUG({

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

@@ -2484,11 +2484,10 @@ bool SIMemoryLegalizer::expandLoad(const SIMemOpInfo &MOI,
   // Atomic instructions already bypass caches to the scope specified by the
   // SyncScope operand. Only non-atomic volatile and nontemporal/last-use
   // instructions need additional treatment.
-  // SyncScope operand. Only non-atomic volatile and nontemporal instructions
-  // need additional treatment.
-  Changed |= CC->enableVolatileAndOrNonTemporal(MI, MOI.getInstrAddrSpace(),
-                                                SIMemOp::LOAD, MOI.isVolatile(),
-                                                MOI.isNonTemporal());
+  Changed |= CC->enableVolatileAndOrNonTemporal(
+      MI, MOI.getInstrAddrSpace(), SIMemOp::LOAD, MOI.isVolatile(),
+      MOI.isNonTemporal(), MOI.isLastUse());
+
   return Changed;
 }