Overload the function CallLowering::determineAndHandleAssignments() with

a CCState argument.

Author: Jun Wang

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

@@ -407,6 +407,12 @@ class CallLowering {
       CallingConv::ID CallConv, bool IsVarArg,
       ArrayRef<Register> ThisReturnRegs = std::nullopt) const;
 
+  bool determineAndHandleAssignments(
+      ValueHandler &Handler, ValueAssigner &Assigner,
+      SmallVectorImpl<ArgInfo> &Args, MachineIRBuilder &MIRBuilder,
+      CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,
+      ArrayRef<Register> ThisReturnRegs = std::nullopt) const;
+
   /// Use \p Handler to insert code to handle the argument/return values
   /// represented by \p Args. It's expected determineAssignments previously
   /// processed these arguments to populate \p CCState and \p ArgLocs.

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

@@ -628,6 +628,19 @@ bool CallLowering::determineAndHandleAssignments(
                            ThisReturnRegs);
 }
 
+bool CallLowering::determineAndHandleAssignments(
+    ValueHandler &Handler, ValueAssigner &Assigner,
+    SmallVectorImpl<ArgInfo> &Args, MachineIRBuilder &MIRBuilder,
+    CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,
+    ArrayRef<Register> ThisReturnRegs) const {
+
+  if (!determineAssignments(Assigner, Args, CCInfo))
+    return false;
+
+  return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
+                           ThisReturnRegs);
+}
+
 static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags) {
   if (Flags.isSExt())
     return TargetOpcode::G_SEXT;

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

@@ -317,35 +317,6 @@ bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
   return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg));
 }
 
-/// Replace CallLowering::determineAndHandleAssignments() because we need to
-/// reserve ScratchRSrcReg when necessary.
-/// TODO: Investigate if reserving ScratchRSrcReg can be moved to calling conv
-/// functions. If so, then this function is not needed anymore -- we can just
-/// use CallLowering::determineAndHandleAssignments() as before.
-bool AMDGPUCallLowering::determineAndHandleAssignmentsLocal(
-    ValueHandler &Handler, ValueAssigner &Assigner,
-    SmallVectorImpl<ArgInfo> &Args, MachineIRBuilder &MIRBuilder,
-    CallingConv::ID CallConv, bool IsVarArg) const {
-
-  MachineFunction &MF = MIRBuilder.getMF();
-  const Function &F = MF.getFunction();
-
-  SmallVector<CCValAssign, 16> ArgLocs;
-
-  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
-
-  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
-  if (!ST.enableFlatScratch()) {
-    SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
-    CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
-  }
-
-  if (!determineAssignments(Assigner, Args, CCInfo))
-    return false;
-
-  return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder);
-}
-
 /// Lower the return value for the already existing \p Ret. This assumes that
 /// \p B's insertion point is correct.
 bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
@@ -409,8 +380,16 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
   OutgoingValueAssigner Assigner(AssignFn);
   AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret);
 
-  return determineAndHandleAssignmentsLocal(RetHandler, Assigner, SplitRetInfos,
-                                            B, CC, F.isVarArg());
+  SmallVector<CCValAssign, 16> ArgLocs;
+  CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
+
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+  if (!ST.enableFlatScratch()) {
+    SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
+    CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
+  }
+  return determineAndHandleAssignments(RetHandler, Assigner, SplitRetInfos, B,
+                                       CCInfo, ArgLocs);
 }
 
 bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,
@@ -1575,9 +1554,17 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                                       Info.IsVarArg);
     IncomingValueAssigner Assigner(RetAssignFn);
     CallReturnHandler Handler(MIRBuilder, MRI, MIB);
-    if (!determineAndHandleAssignmentsLocal(Handler, Assigner, InArgs,
-                                            MIRBuilder, Info.CallConv,
-                                            Info.IsVarArg))
+
+    SmallVector<CCValAssign, 16> ArgLocs;
+    CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
+
+    const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+    if (!ST.enableFlatScratch()) {
+      SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
+      CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
+    }
+    if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
+                                       CCInfo, ArgLocs))
       return false;
   }
 

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h

@@ -37,13 +37,6 @@ class AMDGPUCallLowering final : public CallLowering {
   bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
                       ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
 
-  bool determineAndHandleAssignmentsLocal(ValueHandler &Handler,
-                                          ValueAssigner &Assigner,
-                                          SmallVectorImpl<ArgInfo> &Args,
-                                          MachineIRBuilder &MIRBuilder,
-                                          CallingConv::ID CallConv,
-                                          bool IsVarArg) const;
-
 public:
   AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
 

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -16039,9 +16039,7 @@ static bool isCopyFromRegForI1Return(const SDNode *N) {
     N3 = N3->getOperand(0).getNode();
   } while (N3->getOpcode() == ISD::CopyFromReg);
 
-  if (N3->getOpcode() != ISD::CALLSEQ_END)
-    return false;
-  return true;
+  return N3->getOpcode() == ISD::CALLSEQ_END;
 }
 
 bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode *N,