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Karthi Kandasamyalexdeucher
Karthi Kandasamy
authored and
alexdeucher
committed
drm/amd/display: Update dc_tiling_info union to structure
[WHY] The `dc_tiling_info` union previously did not have a field to specify the active GFX format, assuming only one format would be used per DCN version. from DCN4+, support for switching between different GFX formats is introduced, requiring a way to track which format is currently in use. [HOW] Updated the `dc_tiling_info` union to include a new field that explicitly indicates the currently used GFX format. This allows the system to determine the active GFX format and take the correct programming path accordingly. [Description] The union `dc_tiling_info` has been updated to support multiple GFX formats by adding a new field for identifying the active format. This update ensures that the correct programming path is followed based on the selected format. All references to `dc_tiling_info` in the codebase have been updated to reflect the new structure. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Karthi Kandasamy <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-124
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20 files changed

+136
-124
lines changed

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier
177177
return AMD_FMT_MOD_GET(TILE, modifier);
178178
}
179179

180-
static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
180+
static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,
181181
uint64_t tiling_flags)
182182
{
183183
/* Fill GFX8 params */
@@ -210,7 +210,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_inf
210210
}
211211

212212
static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
213-
union dc_tiling_info *tiling_info)
213+
struct dc_tiling_info *tiling_info)
214214
{
215215
/* Fill GFX9 params */
216216
tiling_info->gfx9.num_pipes =
@@ -231,7 +231,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgp
231231
}
232232

233233
static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
234-
union dc_tiling_info *tiling_info,
234+
struct dc_tiling_info *tiling_info,
235235
uint64_t modifier)
236236
{
237237
unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
@@ -261,7 +261,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amd
261261
static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
262262
const enum surface_pixel_format format,
263263
const enum dc_rotation_angle rotation,
264-
const union dc_tiling_info *tiling_info,
264+
const struct dc_tiling_info *tiling_info,
265265
const struct dc_plane_dcc_param *dcc,
266266
const struct dc_plane_address *address,
267267
const struct plane_size *plane_size)
@@ -308,7 +308,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg
308308
const enum surface_pixel_format format,
309309
const enum dc_rotation_angle rotation,
310310
const struct plane_size *plane_size,
311-
union dc_tiling_info *tiling_info,
311+
struct dc_tiling_info *tiling_info,
312312
struct dc_plane_dcc_param *dcc,
313313
struct dc_plane_address *address)
314314
{
@@ -358,7 +358,7 @@ static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amd
358358
const enum surface_pixel_format format,
359359
const enum dc_rotation_angle rotation,
360360
const struct plane_size *plane_size,
361-
union dc_tiling_info *tiling_info,
361+
struct dc_tiling_info *tiling_info,
362362
struct dc_plane_dcc_param *dcc,
363363
struct dc_plane_address *address)
364364
{
@@ -834,7 +834,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
834834
const enum surface_pixel_format format,
835835
const enum dc_rotation_angle rotation,
836836
const uint64_t tiling_flags,
837-
union dc_tiling_info *tiling_info,
837+
struct dc_tiling_info *tiling_info,
838838
struct plane_size *plane_size,
839839
struct dc_plane_dcc_param *dcc,
840840
struct dc_plane_address *address,

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
4747
const enum surface_pixel_format format,
4848
const enum dc_rotation_angle rotation,
4949
const uint64_t tiling_flags,
50-
union dc_tiling_info *tiling_info,
50+
struct dc_tiling_info *tiling_info,
5151
struct plane_size *plane_size,
5252
struct dc_plane_dcc_param *dcc,
5353
struct dc_plane_address *address,

‎drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2555,7 +2555,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc,
25552555

25562556

25572557
if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2558-
sizeof(union dc_tiling_info)) != 0) {
2558+
sizeof(struct dc_tiling_info)) != 0) {
25592559
update_flags->bits.swizzle_change = 1;
25602560
elevate_update_type(&update_type, UPDATE_TYPE_MED);
25612561

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,7 +1306,7 @@ struct dc_plane_state {
13061306
struct rect clip_rect;
13071307

13081308
struct plane_size plane_size;
1309-
union dc_tiling_info tiling_info;
1309+
struct dc_tiling_info tiling_info;
13101310

13111311
struct dc_plane_dcc_param dcc;
13121312

@@ -1377,7 +1377,7 @@ struct dc_plane_state {
13771377

13781378
struct dc_plane_info {
13791379
struct plane_size plane_size;
1380-
union dc_tiling_info tiling_info;
1380+
struct dc_tiling_info tiling_info;
13811381
struct dc_plane_dcc_param dcc;
13821382
enum surface_pixel_format format;
13831383
enum dc_rotation_angle rotation;

‎drivers/gpu/drm/amd/display/dc/dc_hw_types.h

Lines changed: 94 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -341,89 +341,101 @@ enum swizzle_mode_addr3_values {
341341
DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX
342342
};
343343

344-
union dc_tiling_info {
345-
346-
struct {
347-
/* Specifies the number of memory banks for tiling
348-
* purposes.
349-
* Only applies to 2D and 3D tiling modes.
350-
* POSSIBLE VALUES: 2,4,8,16
351-
*/
352-
unsigned int num_banks;
353-
/* Specifies the number of tiles in the x direction
354-
* to be incorporated into the same bank.
355-
* Only applies to 2D and 3D tiling modes.
356-
* POSSIBLE VALUES: 1,2,4,8
357-
*/
358-
unsigned int bank_width;
359-
unsigned int bank_width_c;
360-
/* Specifies the number of tiles in the y direction to
361-
* be incorporated into the same bank.
362-
* Only applies to 2D and 3D tiling modes.
363-
* POSSIBLE VALUES: 1,2,4,8
364-
*/
365-
unsigned int bank_height;
366-
unsigned int bank_height_c;
367-
/* Specifies the macro tile aspect ratio. Only applies
368-
* to 2D and 3D tiling modes.
369-
*/
370-
unsigned int tile_aspect;
371-
unsigned int tile_aspect_c;
372-
/* Specifies the number of bytes that will be stored
373-
* contiguously for each tile.
374-
* If the tile data requires more storage than this
375-
* amount, it is split into multiple slices.
376-
* This field must not be larger than
377-
* GB_ADDR_CONFIG.DRAM_ROW_SIZE.
378-
* Only applies to 2D and 3D tiling modes.
379-
* For color render targets, TILE_SPLIT >= 256B.
380-
*/
381-
enum tile_split_values tile_split;
382-
enum tile_split_values tile_split_c;
383-
/* Specifies the addressing within a tile.
384-
* 0x0 - DISPLAY_MICRO_TILING
385-
* 0x1 - THIN_MICRO_TILING
386-
* 0x2 - DEPTH_MICRO_TILING
387-
* 0x3 - ROTATED_MICRO_TILING
388-
*/
389-
enum tile_mode_values tile_mode;
390-
enum tile_mode_values tile_mode_c;
391-
/* Specifies the number of pipes and how they are
392-
* interleaved in the surface.
393-
* Refer to memory addressing document for complete
394-
* details and constraints.
395-
*/
396-
unsigned int pipe_config;
397-
/* Specifies the tiling mode of the surface.
398-
* THIN tiles use an 8x8x1 tile size.
399-
* THICK tiles use an 8x8x4 tile size.
400-
* 2D tiling modes rotate banks for successive Z slices
401-
* 3D tiling modes rotate pipes and banks for Z slices
402-
* Refer to memory addressing document for complete
403-
* details and constraints.
404-
*/
405-
enum array_mode_values array_mode;
406-
} gfx8;
344+
enum dc_gfxversion {
345+
DcGfxVersion7 = 0,
346+
DcGfxVersion8,
347+
DcGfxVersion9,
348+
DcGfxVersion10,
349+
DcGfxVersion11,
350+
DcGfxAddr3,
351+
DcGfxVersionUnknown
352+
};
353+
354+
struct dc_tiling_info {
355+
unsigned int gfxversion; // Specifies which part of the union to use. Must use DalGfxVersion enum
356+
union {
357+
struct {
358+
/* Specifies the number of memory banks for tiling
359+
* purposes.
360+
* Only applies to 2D and 3D tiling modes.
361+
* POSSIBLE VALUES: 2,4,8,16
362+
*/
363+
unsigned int num_banks;
364+
/* Specifies the number of tiles in the x direction
365+
* to be incorporated into the same bank.
366+
* Only applies to 2D and 3D tiling modes.
367+
* POSSIBLE VALUES: 1,2,4,8
368+
*/
369+
unsigned int bank_width;
370+
unsigned int bank_width_c;
371+
/* Specifies the number of tiles in the y direction to
372+
* be incorporated into the same bank.
373+
* Only applies to 2D and 3D tiling modes.
374+
* POSSIBLE VALUES: 1,2,4,8
375+
*/
376+
unsigned int bank_height;
377+
unsigned int bank_height_c;
378+
/* Specifies the macro tile aspect ratio. Only applies
379+
* to 2D and 3D tiling modes.
380+
*/
381+
unsigned int tile_aspect;
382+
unsigned int tile_aspect_c;
383+
/* Specifies the number of bytes that will be stored
384+
* contiguously for each tile.
385+
* If the tile data requires more storage than this
386+
* amount, it is split into multiple slices.
387+
* This field must not be larger than
388+
* GB_ADDR_CONFIG.DRAM_ROW_SIZE.
389+
* Only applies to 2D and 3D tiling modes.
390+
* For color render targets, TILE_SPLIT >= 256B.
391+
*/
392+
enum tile_split_values tile_split;
393+
enum tile_split_values tile_split_c;
394+
/* Specifies the addressing within a tile.
395+
* 0x0 - DISPLAY_MICRO_TILING
396+
* 0x1 - THIN_MICRO_TILING
397+
* 0x2 - DEPTH_MICRO_TILING
398+
* 0x3 - ROTATED_MICRO_TILING
399+
*/
400+
enum tile_mode_values tile_mode;
401+
enum tile_mode_values tile_mode_c;
402+
/* Specifies the number of pipes and how they are
403+
* interleaved in the surface.
404+
* Refer to memory addressing document for complete
405+
* details and constraints.
406+
*/
407+
unsigned int pipe_config;
408+
/* Specifies the tiling mode of the surface.
409+
* THIN tiles use an 8x8x1 tile size.
410+
* THICK tiles use an 8x8x4 tile size.
411+
* 2D tiling modes rotate banks for successive Z slices
412+
* 3D tiling modes rotate pipes and banks for Z slices
413+
* Refer to memory addressing document for complete
414+
* details and constraints.
415+
*/
416+
enum array_mode_values array_mode;
417+
} gfx8;
407418

408-
struct {
409-
enum swizzle_mode_values swizzle;
410-
unsigned int num_pipes;
411-
unsigned int max_compressed_frags;
412-
unsigned int pipe_interleave;
413-
414-
unsigned int num_banks;
415-
unsigned int num_shader_engines;
416-
unsigned int num_rb_per_se;
417-
bool shaderEnable;
418-
419-
bool meta_linear;
420-
bool rb_aligned;
421-
bool pipe_aligned;
422-
unsigned int num_pkrs;
423-
} gfx9;/*gfx9, gfx10 and above*/
424-
struct {
425-
enum swizzle_mode_addr3_values swizzle;
426-
} gfx_addr3;/*gfx with addr3 and above*/
419+
struct {
420+
enum swizzle_mode_values swizzle;
421+
unsigned int num_pipes;
422+
unsigned int max_compressed_frags;
423+
unsigned int pipe_interleave;
424+
425+
unsigned int num_banks;
426+
unsigned int num_shader_engines;
427+
unsigned int num_rb_per_se;
428+
bool shaderEnable;
429+
430+
bool meta_linear;
431+
bool rb_aligned;
432+
bool pipe_aligned;
433+
unsigned int num_pkrs;
434+
} gfx9;/*gfx9, gfx10 and above*/
435+
struct {
436+
enum swizzle_mode_addr3_values swizzle;
437+
} gfx_addr3;/*gfx with addr3 and above*/
438+
};
427439
};
428440

429441
/* Rotation angle */

‎drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ static enum mi_bits_per_pixel get_mi_bpp(
9898
}
9999

100100
static enum mi_tiling_format get_mi_tiling(
101-
union dc_tiling_info *tiling_info)
101+
struct dc_tiling_info *tiling_info)
102102
{
103103
switch (tiling_info->gfx8.array_mode) {
104104
case DC_ARRAY_1D_TILED_THIN1:
@@ -133,7 +133,7 @@ static bool is_vert_scan(enum dc_rotation_angle rotation)
133133
static void dce_mi_program_pte_vm(
134134
struct mem_input *mi,
135135
enum surface_pixel_format format,
136-
union dc_tiling_info *tiling_info,
136+
struct dc_tiling_info *tiling_info,
137137
enum dc_rotation_angle rotation)
138138
{
139139
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
@@ -430,7 +430,7 @@ static void dce120_mi_program_display_marks(struct mem_input *mi,
430430
}
431431

432432
static void program_tiling(
433-
struct dce_mem_input *dce_mi, const union dc_tiling_info *info)
433+
struct dce_mem_input *dce_mi, const struct dc_tiling_info *info)
434434
{
435435
if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
436436
REG_UPDATE_6(GRPH_CONTROL,
@@ -650,7 +650,7 @@ static void dce_mi_clear_tiling(
650650
static void dce_mi_program_surface_config(
651651
struct mem_input *mi,
652652
enum surface_pixel_format format,
653-
union dc_tiling_info *tiling_info,
653+
struct dc_tiling_info *tiling_info,
654654
struct plane_size *plane_size,
655655
enum dc_rotation_angle rotation,
656656
struct dc_plane_dcc_param *dcc,
@@ -670,7 +670,7 @@ static void dce_mi_program_surface_config(
670670
static void dce60_mi_program_surface_config(
671671
struct mem_input *mi,
672672
enum surface_pixel_format format,
673-
union dc_tiling_info *tiling_info,
673+
struct dc_tiling_info *tiling_info,
674674
struct plane_size *plane_size,
675675
enum dc_rotation_angle rotation, /* not used in DCE6 */
676676
struct dc_plane_dcc_param *dcc,

‎drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ static void enable(struct dce_mem_input *mem_input110)
162162

163163
static void program_tiling(
164164
struct dce_mem_input *mem_input110,
165-
const union dc_tiling_info *info,
165+
const struct dc_tiling_info *info,
166166
const enum surface_pixel_format pixel_format)
167167
{
168168
uint32_t value = 0;
@@ -523,7 +523,7 @@ static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
523523

524524
/* Helper to get table entry from surface info */
525525
static const unsigned int *get_dvmm_hw_setting(
526-
union dc_tiling_info *tiling_info,
526+
struct dc_tiling_info *tiling_info,
527527
enum surface_pixel_format format,
528528
bool chroma)
529529
{
@@ -563,7 +563,7 @@ static const unsigned int *get_dvmm_hw_setting(
563563
static void dce_mem_input_v_program_pte_vm(
564564
struct mem_input *mem_input,
565565
enum surface_pixel_format format,
566-
union dc_tiling_info *tiling_info,
566+
struct dc_tiling_info *tiling_info,
567567
enum dc_rotation_angle rotation)
568568
{
569569
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
@@ -636,7 +636,7 @@ static void dce_mem_input_v_program_pte_vm(
636636
static void dce_mem_input_v_program_surface_config(
637637
struct mem_input *mem_input,
638638
enum surface_pixel_format format,
639-
union dc_tiling_info *tiling_info,
639+
struct dc_tiling_info *tiling_info,
640640
struct plane_size *plane_size,
641641
enum dc_rotation_angle rotation,
642642
struct dc_plane_dcc_param *dcc,

‎drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ void hubp1_vready_workaround(struct hubp *hubp,
140140

141141
void hubp1_program_tiling(
142142
struct hubp *hubp,
143-
const union dc_tiling_info *info,
143+
const struct dc_tiling_info *info,
144144
const enum surface_pixel_format pixel_format)
145145
{
146146
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -549,7 +549,7 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
549549
void hubp1_program_surface_config(
550550
struct hubp *hubp,
551551
enum surface_pixel_format format,
552-
union dc_tiling_info *tiling_info,
552+
struct dc_tiling_info *tiling_info,
553553
struct plane_size *plane_size,
554554
enum dc_rotation_angle rotation,
555555
struct dc_plane_dcc_param *dcc,

‎drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -706,7 +706,7 @@ struct dcn10_hubp {
706706
void hubp1_program_surface_config(
707707
struct hubp *hubp,
708708
enum surface_pixel_format format,
709-
union dc_tiling_info *tiling_info,
709+
struct dc_tiling_info *tiling_info,
710710
struct plane_size *plane_size,
711711
enum dc_rotation_angle rotation,
712712
struct dc_plane_dcc_param *dcc,
@@ -739,7 +739,7 @@ void hubp1_program_rotation(
739739

740740
void hubp1_program_tiling(
741741
struct hubp *hubp,
742-
const union dc_tiling_info *info,
742+
const struct dc_tiling_info *info,
743743
const enum surface_pixel_format pixel_format);
744744

745745
void hubp1_dcc_control(struct hubp *hubp,

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