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Samson Tamalexdeucher
Samson Tam
authored and
alexdeucher
committed
drm/amd/display: Enable ISHARP support for DCN401
[Why] Enable sharpener support for DCN401 [How] - Removed memcmp check that was preventing ISHARP from being enabled. - Add missing ISHARP register defines, masks, and writes. - Add programming of Blur and Scale coefficients. - Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel - format - Only enable ISHARP for YUV420 - Add disabling of ISHARP - Add debug flags and registry keys for debugging ISHARP. - Set default to medium level Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Samson Tam <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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8 files changed

+223
-65
lines changed

8 files changed

+223
-65
lines changed

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,6 +1040,7 @@ struct dc_debug_options {
10401040
unsigned int force_cositing;
10411041
unsigned int disable_spl;
10421042
unsigned int force_easf;
1043+
unsigned int force_sharpness;
10431044
unsigned int force_lls;
10441045
};
10451046

‎drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -134,16 +134,25 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
134134
spl_in->prefer_easf = false;
135135
else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)
136136
spl_in->disable_easf = true;
137-
// Translate adaptive sharpening preference
138-
spl_in->adaptive_sharpness.enable = plane_state->adaptive_sharpness_en;
139-
if (plane_state->sharpnessX1000 == 0) {
140-
spl_in->adaptive_sharpness.enable = false;
141-
} else if (plane_state->sharpnessX1000 < 999) {
142-
spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
143-
} else if (plane_state->sharpnessX1000 < 1999) {
144-
spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
145-
} else { // Any other value is high sharpness
146-
spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
137+
/* Translate adaptive sharpening preference */
138+
if (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 0) {
139+
spl_in->adaptive_sharpness.enable = (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 1) ? true : false;
140+
if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 2)
141+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
142+
else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 3)
143+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
144+
else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness >= 4)
145+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
146+
} else {
147+
spl_in->adaptive_sharpness.enable = plane_state->adaptive_sharpness_en;
148+
if (plane_state->sharpnessX1000 == 0)
149+
spl_in->adaptive_sharpness.enable = false;
150+
else if (plane_state->sharpnessX1000 < 999)
151+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
152+
else if (plane_state->sharpnessX1000 < 1999)
153+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
154+
else // Any other value is high sharpness
155+
spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
147156
}
148157
// Translate linear light scaling preference
149158
if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)

‎drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

Lines changed: 116 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -949,6 +949,9 @@ static void dpp401_dscl_set_isharp_filter(
949949
{
950950
int level;
951951
uint32_t filter_data;
952+
if (filter == NULL)
953+
return;
954+
952955
REG_UPDATE(ISHARP_DELTA_CTRL,
953956
ISHARP_DELTA_LUT_HOST_SELECT, 0);
954957
for (level = 0; level < NUM_LEVELS; level++) {
@@ -972,41 +975,121 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base,
972975
const struct scaler_data *scl_data)
973976
{
974977
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
975-
const struct dscl_prog_data *data;
976-
977-
if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
978-
return;
979978

980979
PERF_TRACE();
981-
dpp->scl_data = *scl_data;
982-
data = &scl_data->dscl_prog_data;
983-
984-
REG_SET(ISHARP_MODE, 0, ISHARP_EN, data->isharp_en);
985-
986-
REG_SET(ISHARP_MODE, 0, ISHARP_NOISEDET_EN, data->isharp_noise_det.enable);
987-
REG_SET(ISHARP_MODE, 0, ISHARP_NOISEDET_MODE, data->isharp_noise_det.mode);
988-
REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_UTHRE, data->isharp_noise_det.uthreshold);
989-
REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_DTHRE, data->isharp_noise_det.dthreshold);
990-
REG_SET(ISHARP_MODE, 0, ISHARP_NOISEDET_MODE, data->isharp_noise_det.mode);
991-
REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_UTHRE, data->isharp_noise_det.uthreshold);
992-
REG_SET(ISHARP_NOISEDET_THRESHOLD, 0, ISHARP_NOISEDET_DTHRE, data->isharp_noise_det.dthreshold);
993-
REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_START_IN, data->isharp_noise_det.pwl_start_in);
994-
REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_END_IN, data->isharp_noise_det.pwl_end_in);
995-
REG_SET(ISHARP_NOISE_GAIN_PWL, 0, ISHARP_NOISEDET_PWL_SLOPE, data->isharp_noise_det.pwl_slope);
996-
997-
REG_SET(ISHARP_MODE, 0, ISHARP_LBA_MODE, data->isharp_lba.mode);
998-
// TODO: ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG
999-
REG_SET(ISHARP_MODE, 0, ISHARP_FMT_MODE, data->isharp_fmt.mode);
1000-
REG_SET(ISHARP_MODE, 0, ISHARP_FMT_NORM, data->isharp_fmt.norm);
1001-
1002-
dpp401_dscl_set_isharp_filter(dpp, data->isharp_delta);
1003-
1004-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_EN_P, data->isharp_nldelta_sclip.enable_p);
1005-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_PIVOT_P, data->isharp_nldelta_sclip.pivot_p);
1006-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_SLOPE_P, data->isharp_nldelta_sclip.slope_p);
1007-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_EN_N, data->isharp_nldelta_sclip.enable_n);
1008-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_PIVOT_N, data->isharp_nldelta_sclip.pivot_n);
1009-
REG_SET(ISHARP_NLDELTA_SOFT_CLIP, 0, ISHARP_NLDELTA_SCLIP_SLOPE_N, data->isharp_nldelta_sclip.slope_n);
980+
/* ISHARP_EN */
981+
REG_UPDATE(ISHARP_MODE,
982+
ISHARP_EN, scl_data->dscl_prog_data.isharp_en);
983+
/* ISHARP_NOISEDET_EN */
984+
REG_UPDATE(ISHARP_MODE,
985+
ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable);
986+
/* ISHARP_NOISEDET_MODE */
987+
REG_UPDATE(ISHARP_MODE,
988+
ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);
989+
/* ISHARP_NOISEDET_UTHRE */
990+
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
991+
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);
992+
/* ISHARP_NOISEDET_DTHRE */
993+
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
994+
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
995+
REG_UPDATE(ISHARP_MODE,
996+
ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);
997+
/* ISHARP_NOISEDET_UTHRE */
998+
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
999+
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);
1000+
/* ISHARP_NOISEDET_DTHRE */
1001+
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
1002+
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
1003+
/* ISHARP_NOISEDET_PWL_START_IN */
1004+
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
1005+
ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in);
1006+
/* ISHARP_NOISEDET_PWL_END_IN */
1007+
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
1008+
ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in);
1009+
/* ISHARP_NOISEDET_PWL_SLOPE */
1010+
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
1011+
ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);
1012+
/* ISHARP_LBA_MODE */
1013+
REG_UPDATE(ISHARP_MODE,
1014+
ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode);
1015+
/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */
1016+
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
1017+
ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0]);
1018+
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
1019+
ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0]);
1020+
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
1021+
ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);
1022+
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
1023+
ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1]);
1024+
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
1025+
ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1]);
1026+
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
1027+
ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);
1028+
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
1029+
ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2]);
1030+
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
1031+
ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2]);
1032+
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
1033+
ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);
1034+
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
1035+
ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3]);
1036+
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
1037+
ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3]);
1038+
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
1039+
ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);
1040+
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
1041+
ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4]);
1042+
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
1043+
ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4]);
1044+
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
1045+
ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);
1046+
REG_UPDATE(ISHARP_LBA_PWL_SEG5,
1047+
ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5]);
1048+
REG_UPDATE(ISHARP_LBA_PWL_SEG5,
1049+
ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);
1050+
1051+
/* ISHARP_FMT_MODE */
1052+
REG_UPDATE(ISHARP_MODE,
1053+
ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode);
1054+
/* ISHARP_FMT_NORM */
1055+
REG_UPDATE(ISHARP_MODE,
1056+
ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);
1057+
/* ISHARP_DELTA_LUT */
1058+
dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);
1059+
/* ISHARP_NLDELTA_SCLIP_EN_P */
1060+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1061+
ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p);
1062+
/* ISHARP_NLDELTA_SCLIP_PIVOT_P */
1063+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1064+
ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p);
1065+
/* ISHARP_NLDELTA_SCLIP_SLOPE_P */
1066+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1067+
ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p);
1068+
/* ISHARP_NLDELTA_SCLIP_EN_N */
1069+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1070+
ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n);
1071+
/* ISHARP_NLDELTA_SCLIP_PIVOT_N */
1072+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1073+
ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n);
1074+
/* ISHARP_NLDELTA_SCLIP_SLOPE_N */
1075+
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
1076+
ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);
1077+
1078+
/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */
1079+
if (scl_data->dscl_prog_data.isharp_en) {
1080+
if (scl_data->dscl_prog_data.filter_blur_scale_v) {
1081+
dpp401_dscl_set_scaler_filter(
1082+
dpp, scl_data->taps.v_taps,
1083+
SCL_COEF_VERTICAL_BLUR_SCALE,
1084+
scl_data->dscl_prog_data.filter_blur_scale_v);
1085+
}
1086+
if (scl_data->dscl_prog_data.filter_blur_scale_h) {
1087+
dpp401_dscl_set_scaler_filter(
1088+
dpp, scl_data->taps.h_taps,
1089+
SCL_COEF_HORIZONTAL_BLUR_SCALE,
1090+
scl_data->dscl_prog_data.filter_blur_scale_h);
1091+
}
1092+
}
10101093
PERF_TRACE();
10111094
} // dpp401_dscl_program_isharp
10121095
/**

‎drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -387,6 +387,19 @@ bool dcn401_validate_bandwidth(struct dc *dc,
387387
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \
388388
SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \
389389
SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \
390+
SRI_ARR(ISHARP_MODE, DSCL, id), \
391+
SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \
392+
SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \
393+
SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \
394+
SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \
395+
SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \
396+
SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \
397+
SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \
398+
SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \
399+
SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \
400+
SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \
401+
SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \
402+
SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \
390403
SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
391404
SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)
392405

‎drivers/gpu/drm/amd/display/dc/spl/dc_spl.c

Lines changed: 65 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -913,6 +913,25 @@ static void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,
913913
dscl_prog_data->filter_v_c = spl_dscl_get_filter_coeffs_64p(
914914
data->taps.v_taps_c, data->ratios.vert_c);
915915
}
916+
917+
static const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps)
918+
{
919+
if ((taps == 3) || (taps == 4) || (taps == 6))
920+
return spl_get_filter_isharp_bs_4tap_64p();
921+
else {
922+
/* should never happen, bug */
923+
return NULL;
924+
}
925+
}
926+
static void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,
927+
const struct spl_scaler_data *data)
928+
{
929+
dscl_prog_data->filter_blur_scale_h = spl_dscl_get_blur_scale_coeffs_64p(
930+
data->taps.h_taps);
931+
dscl_prog_data->filter_blur_scale_v = spl_dscl_get_blur_scale_coeffs_64p(
932+
data->taps.v_taps);
933+
}
934+
916935
/* Populate dscl prog data structure from scaler data calculated by SPL */
917936
static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_out *spl_out)
918937
{
@@ -1226,10 +1245,18 @@ static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data)
12261245
else if (dscl_prog_data->taps.h_taps == 3)
12271246
dscl_prog_data->isharp_noise_det.mode = 0; // ISHARP_NOISEDET_MODE
12281247
};
1229-
/* Set EASF data */
1248+
/* Set Sharpener data */
12301249
static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,
1231-
struct adaptive_sharpness adp_sharpness)
1250+
struct adaptive_sharpness adp_sharpness, bool enable_isharp,
1251+
enum linear_light_scaling lls_pref, enum spl_pixel_format format,
1252+
const struct spl_scaler_data *data)
12321253
{
1254+
/* Turn off sharpener if not required */
1255+
if (!enable_isharp) {
1256+
dscl_prog_data->isharp_en = 0;
1257+
return;
1258+
}
1259+
12331260
dscl_prog_data->isharp_en = 1; // ISHARP_EN
12341261
dscl_prog_data->isharp_noise_det.enable = 1; // ISHARP_NOISEDET_EN
12351262
// Set ISHARP_NOISEDET_MODE if htaps = 6-tap
@@ -1243,7 +1270,11 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,
12431270
dscl_prog_data->isharp_noise_det.pwl_end_in = 13; // ISHARP_NOISEDET_PWL_END_IN
12441271
dscl_prog_data->isharp_noise_det.pwl_slope = 1623; // ISHARP_NOISEDET_PWL_SLOPE
12451272

1246-
dscl_prog_data->isharp_fmt.mode = 1; // ISHARP_FMT_MODE
1273+
if ((lls_pref == LLS_PREF_NO) && !spl_is_yuv420(format)) /* ISHARP_FMT_MODE */
1274+
dscl_prog_data->isharp_fmt.mode = 1;
1275+
else
1276+
dscl_prog_data->isharp_fmt.mode = 0;
1277+
12471278
dscl_prog_data->isharp_fmt.norm = 0x3C00; // ISHARP_FMT_NORM
12481279
dscl_prog_data->isharp_lba.mode = 0; // ISHARP_LBA_MODE
12491280
// ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0
@@ -1269,7 +1300,7 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,
12691300
// ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5
12701301
dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format
12711302
dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format
1272-
switch (adp_sharpness.sharpness) {
1303+
switch (adp_sharpness.sharpness) {
12731304
case SHARPNESS_LOW:
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dscl_prog_data->isharp_delta = spl_get_filter_isharp_1D_lut_0p5x();
12751306
break;
@@ -1284,17 +1315,28 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,
12841315
}
12851316

12861317
// Program the nldelta soft clip values
1287-
dscl_prog_data->isharp_nldelta_sclip.enable_p = 1; // ISHARP_NLDELTA_SCLIP_EN_P
1288-
dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70; // ISHARP_NLDELTA_SCLIP_PIVOT_P
1289-
dscl_prog_data->isharp_nldelta_sclip.slope_p = 24; // ISHARP_NLDELTA_SCLIP_SLOPE_P
1290-
dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; // ISHARP_NLDELTA_SCLIP_EN_N
1291-
dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70; // ISHARP_NLDELTA_SCLIP_PIVOT_N
1292-
dscl_prog_data->isharp_nldelta_sclip.slope_n = 24; // ISHARP_NLDELTA_SCLIP_SLOPE_N
1318+
if (lls_pref == LLS_PREF_YES) {
1319+
dscl_prog_data->isharp_nldelta_sclip.enable_p = 0; /* ISHARP_NLDELTA_SCLIP_EN_P */
1320+
dscl_prog_data->isharp_nldelta_sclip.pivot_p = 0; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */
1321+
dscl_prog_data->isharp_nldelta_sclip.slope_p = 0; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */
1322+
dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */
1323+
dscl_prog_data->isharp_nldelta_sclip.pivot_n = 71; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */
1324+
dscl_prog_data->isharp_nldelta_sclip.slope_n = 16; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */
1325+
} else {
1326+
dscl_prog_data->isharp_nldelta_sclip.enable_p = 1; /* ISHARP_NLDELTA_SCLIP_EN_P */
1327+
dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */
1328+
dscl_prog_data->isharp_nldelta_sclip.slope_p = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */
1329+
dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */
1330+
dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */
1331+
dscl_prog_data->isharp_nldelta_sclip.slope_n = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */
1332+
}
12931333

12941334
// Set the values as per lookup table
1335+
spl_set_blur_scale_data(dscl_prog_data, data);
12951336
}
12961337
static bool spl_get_isharp_en(struct adaptive_sharpness adp_sharpness,
1297-
int vscale_ratio, int hscale_ratio, struct spl_taps taps)
1338+
int vscale_ratio, int hscale_ratio, struct spl_taps taps,
1339+
enum spl_pixel_format format)
12981340
{
12991341
bool enable_isharp = false;
13001342

@@ -1307,6 +1349,10 @@ static bool spl_get_isharp_en(struct adaptive_sharpness adp_sharpness,
13071349
}
13081350
// Scaling is up to 1:1 (no scaling) or upscaling
13091351

1352+
/* Only apply sharpness to NV12 and not P010 */
1353+
if (format != SPL_PIXEL_FORMAT_420BPP8)
1354+
return enable_isharp;
1355+
13101356
// LB support horizontal taps 4,6 or vertical taps 3, 4, 6
13111357
if (taps.h_taps == 4 || taps.h_taps == 6 ||
13121358
taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6) {
@@ -1342,13 +1388,14 @@ static bool spl_choose_lls_policy(enum spl_pixel_format format,
13421388
return false;
13431389
}
13441390

1345-
/* Caclulate scaler parameters */
1391+
/* Calculate scaler parameters */
13461392
bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out)
13471393
{
13481394
bool res = false;
13491395
bool enable_easf_v = false;
13501396
bool enable_easf_h = false;
13511397
bool lls_enable_easf = true;
1398+
const struct spl_scaler_data *data = &spl_out->scl_data;
13521399
// All SPL calls
13531400
/* recout calculation */
13541401
/* depends on h_active */
@@ -1400,10 +1447,12 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out)
14001447
}
14011448
// Set EASF
14021449
spl_set_easf_data(spl_out->dscl_prog_data, enable_easf_v, enable_easf_h, spl_in->lls_pref,
1403-
spl_in->basic_in.format); // Set iSHARP
1450+
spl_in->basic_in.format);
1451+
// Set iSHARP
14041452
bool enable_isharp = spl_get_isharp_en(spl_in->adaptive_sharpness, vratio, hratio,
1405-
spl_out->scl_data.taps);
1406-
if (enable_isharp)
1407-
spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness);
1453+
spl_out->scl_data.taps, spl_in->basic_in.format);
1454+
spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp,
1455+
spl_in->lls_pref, spl_in->basic_in.format, data);
1456+
14081457
return res;
14091458
}

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