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arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the MPLL clocks aren't changed (as these are reserved for audio). The only exception to this is the GXL S805X package because the 744MHz OPP isn't working correctly there. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 BayLibre SAS
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* Author: Neil Armstrong <[email protected]>
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*/
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/ {
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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11+
opp-125000000 {
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opp-hz = /bits/ 64 <125000000>;
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opp-microvolt = <950000>;
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};
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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opp-microvolt = <950000>;
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};
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opp-285714285 {
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opp-hz = /bits/ 64 <285714285>;
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opp-microvolt = <950000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <950000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <950000>;
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};
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opp-666666666 {
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opp-hz = /bits/ 64 <666666666>;
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opp-microvolt = <950000>;
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};
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opp-744000000 {
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opp-hz = /bits/ 64 <744000000>;
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opp-microvolt = <950000>;
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};
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};
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};
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&apb {
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mali: gpu@c0000 {
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compatible = "arm,mali-450";
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reg = <0x0 0xc0000 0x0 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2";
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operating-points-v2 = <&gpu_opp_table>;
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};
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};

‎arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

Lines changed: 11 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
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*/
55

66
#include "meson-gx.dtsi"
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#include "meson-gx-mali450.dtsi"
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#include <dt-bindings/gpio/meson-gxbb-gpio.h>
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#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
@@ -264,46 +265,6 @@
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};
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};
266267

267-
&apb {
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mali: gpu@c0000 {
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compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
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reg = <0x0 0xc0000 0x0 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
286-
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/*
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* Mali clocking is provided by two identical clock paths
289-
* MALI_0 and MALI_1 muxed to a single clock by a glitch
290-
* free mux to safely change frequency while running.
291-
*/
292-
assigned-clocks = <&clkc CLKID_GP0_PLL>,
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<&clkc CLKID_MALI_0_SEL>,
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<&clkc CLKID_MALI_0>,
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<&clkc CLKID_MALI>; /* Glitch free mux */
296-
assigned-clock-parents = <0>, /* Do Nothing */
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<&clkc CLKID_GP0_PLL>,
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<0>, /* Do Nothing */
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<&clkc CLKID_MALI_0>;
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assigned-clock-rates = <744000000>,
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<0>, /* Do Nothing */
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<744000000>,
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<0>; /* Do Nothing */
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};
305-
};
306-
307268
&cbus {
308269
spifc: spi@8c80 {
309270
compatible = "amlogic,meson-gxbb-spifc";
@@ -386,6 +347,16 @@
386347
clocks = <&clkc CLKID_I2C>;
387348
};
388349

350+
&mali {
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compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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assigned-clocks = <&clkc CLKID_GP0_PLL>;
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assigned-clock-rates = <744000000>;
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};
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389360
&periphs {
390361
pinctrl_periphs: pinctrl@4b0 {
391362
compatible = "amlogic,meson-gxbb-periphs-pinctrl";

‎arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi

Lines changed: 9 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -4,42 +4,14 @@
44
* Author: Neil Armstrong <[email protected]>
55
*/
66

7-
&apb {
8-
mali: gpu@c0000 {
9-
compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
10-
reg = <0x0 0xc0000 0x0 0x40000>;
11-
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
12-
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
13-
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
14-
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
15-
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
16-
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
17-
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
18-
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
19-
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
20-
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
21-
interrupt-names = "gp", "gpmmu", "pp", "pmu",
22-
"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2";
24-
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
25-
clock-names = "bus", "core";
7+
#include "meson-gx-mali450.dtsi"
268

27-
/*
28-
* Mali clocking is provided by two identical clock paths
29-
* MALI_0 and MALI_1 muxed to a single clock by a glitch
30-
* free mux to safely change frequency while running.
31-
*/
32-
assigned-clocks = <&clkc CLKID_GP0_PLL>,
33-
<&clkc CLKID_MALI_0_SEL>,
34-
<&clkc CLKID_MALI_0>,
35-
<&clkc CLKID_MALI>; /* Glitch free mux */
36-
assigned-clock-parents = <0>, /* Do Nothing */
37-
<&clkc CLKID_GP0_PLL>,
38-
<0>, /* Do Nothing */
39-
<&clkc CLKID_MALI_0>;
40-
assigned-clock-rates = <744000000>,
41-
<0>, /* Do Nothing */
42-
<744000000>,
43-
<0>; /* Do Nothing */
44-
};
9+
&mali {
10+
compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
11+
12+
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
13+
clock-names = "bus", "core";
14+
15+
assigned-clocks = <&clkc CLKID_GP0_PLL>;
16+
assigned-clock-rates = <744000000>;
4517
};

‎arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,13 @@
1111
};
1212

1313
/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */
14+
&gpu_opp_table {
15+
opp-744000000 {
16+
status = "disabled";
17+
};
18+
};
19+
1420
&mali {
15-
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
16-
<&clkc CLKID_MALI_0>,
17-
<&clkc CLKID_MALI>; /* Glitch free mux */
18-
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
19-
<0>, /* Do Nothing */
20-
<&clkc CLKID_MALI_0>;
21-
assigned-clock-rates = <0>, /* Do Nothing */
22-
<666666666>,
23-
<0>; /* Do Nothing */
21+
/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
2423
};

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