@@ -236,7 +236,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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if (mode & EMIT_INVALIDATE ) {
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u32 flags = 0 ;
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- u32 * cs ;
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+ u32 * cs , count ;
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flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE ;
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flags |= PIPE_CONTROL_TLB_INVALIDATE ;
@@ -254,7 +254,12 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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if (engine -> class == COMPUTE_CLASS )
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flags &= ~PIPE_CONTROL_3D_FLAGS ;
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- cs = intel_ring_begin (rq , 8 + 4 );
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+ if (!HAS_FLAT_CCS (rq -> engine -> i915 ))
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+ count = 8 + 4 ;
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+ else
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+ count = 8 ;
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+
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+ cs = intel_ring_begin (rq , count );
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if (IS_ERR (cs ))
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return PTR_ERR (cs );
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@@ -267,8 +272,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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cs = gen8_emit_pipe_control (cs , flags , LRC_PPHWSP_SCRATCH_ADDR );
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- /* hsdes: 1809175790 */
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- cs = gen12_emit_aux_table_inv (GEN12_GFX_CCS_AUX_NV , cs );
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+ if (!HAS_FLAT_CCS (rq -> engine -> i915 )) {
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+ /* hsdes: 1809175790 */
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+ cs = gen12_emit_aux_table_inv (GEN12_GFX_CCS_AUX_NV , cs );
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+ }
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* cs ++ = preparser_disable (false);
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intel_ring_advance (rq , cs );
@@ -283,12 +290,15 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
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u32 cmd , * cs ;
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cmd = 4 ;
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- if (mode & EMIT_INVALIDATE )
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+ if (mode & EMIT_INVALIDATE ) {
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cmd += 2 ;
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- if (mode & EMIT_INVALIDATE )
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- aux_inv = rq -> engine -> mask & ~BIT (BCS0 );
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- if (aux_inv )
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- cmd += 2 * hweight32 (aux_inv ) + 2 ;
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+
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+ if (!HAS_FLAT_CCS (rq -> engine -> i915 )) {
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+ aux_inv = rq -> engine -> mask & ~BIT (BCS0 );
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+ if (aux_inv )
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+ cmd += 2 * hweight32 (aux_inv ) + 2 ;
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+ }
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+ }
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cs = intel_ring_begin (rq , cmd );
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if (IS_ERR (cs ))
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