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Aviv Hellerrleon
Aviv Heller
authored and
rleon
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net/mlx5: Add HW interfaces used by LAG
Exposed LAG commands enum and layouts: - CREATE_LAG HW enters LAG mode: RoCE traffic from port two is received on PF0 core dev. Allows to set tx_affinity (tx port) for QPs and TISes. Allows to port remap QPs and TISes, overriding their tx_affinity behavior. - MODIFY_LAG Remap QPs and TISes to another port. - QUERY_LAG Query whether LAG mode is active. - DESTROY_LAG HW exits LAG mode, returning to non-LAG behavior. - CREATE_VPORT_LAG Merge Ethernet flow steering, such that traffic received on port two jumps to PF0 root flow table. Available only in LAG mode. - DESTROY_VPORT_LAG Ethernet flow steering returns to non-LAG behavior. Caps added: - lag_master Driver is in charge of managing the LAG. This is currently the only option. - num_lag_ports LAG is supported only if this field's value is 2. Other fields: - QP/TIS tx port affinity During LAG, this field controls on which port a QP or TIS resides. - TIS strict tx affinity When this field is set, the TIS will not be subject to port remap by CREATE_LAG/MODIFY_LAG. - LAG demux flow table Flow table used for redirecting non user-space traffic back to PF1 root flow table, if the packet was received on port two. Signed-off-by: Aviv Heller <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: Leon Romanovsky <[email protected]>
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‎drivers/net/ethernet/mellanox/mlx5/core/cmd.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -285,6 +285,8 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
285285
case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
286286
case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
287287
case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
288+
case MLX5_CMD_OP_DESTROY_LAG:
289+
case MLX5_CMD_OP_DESTROY_VPORT_LAG:
288290
case MLX5_CMD_OP_DESTROY_TIR:
289291
case MLX5_CMD_OP_DESTROY_SQ:
290292
case MLX5_CMD_OP_DESTROY_RQ:
@@ -376,6 +378,10 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
376378
case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
377379
case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
378380
case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
381+
case MLX5_CMD_OP_CREATE_LAG:
382+
case MLX5_CMD_OP_MODIFY_LAG:
383+
case MLX5_CMD_OP_QUERY_LAG:
384+
case MLX5_CMD_OP_CREATE_VPORT_LAG:
379385
case MLX5_CMD_OP_CREATE_TIR:
380386
case MLX5_CMD_OP_MODIFY_TIR:
381387
case MLX5_CMD_OP_QUERY_TIR:
@@ -514,6 +520,12 @@ const char *mlx5_command_str(int command)
514520
MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
515521
MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
516522
MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
523+
MLX5_COMMAND_STR_CASE(CREATE_LAG);
524+
MLX5_COMMAND_STR_CASE(MODIFY_LAG);
525+
MLX5_COMMAND_STR_CASE(QUERY_LAG);
526+
MLX5_COMMAND_STR_CASE(DESTROY_LAG);
527+
MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
528+
MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
517529
MLX5_COMMAND_STR_CASE(CREATE_TIR);
518530
MLX5_COMMAND_STR_CASE(MODIFY_TIR);
519531
MLX5_COMMAND_STR_CASE(DESTROY_TIR);

‎include/linux/mlx5/mlx5_ifc.h

Lines changed: 159 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,12 @@ enum {
174174
MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
175175
MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176176
MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
177+
MLX5_CMD_OP_CREATE_LAG = 0x840,
178+
MLX5_CMD_OP_MODIFY_LAG = 0x841,
179+
MLX5_CMD_OP_QUERY_LAG = 0x842,
180+
MLX5_CMD_OP_DESTROY_LAG = 0x843,
181+
MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
182+
MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
177183
MLX5_CMD_OP_CREATE_TIR = 0x900,
178184
MLX5_CMD_OP_MODIFY_TIR = 0x901,
179185
MLX5_CMD_OP_DESTROY_TIR = 0x902,
@@ -884,7 +890,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
884890
u8 pad_tx_eth_packet[0x1];
885891
u8 reserved_at_263[0x8];
886892
u8 log_bf_reg_size[0x5];
887-
u8 reserved_at_270[0x10];
893+
894+
u8 reserved_at_270[0xb];
895+
u8 lag_master[0x1];
896+
u8 num_lag_ports[0x4];
888897

889898
u8 reserved_at_280[0x10];
890899
u8 max_wqe_sz_sq[0x10];
@@ -1918,7 +1927,7 @@ enum {
19181927

19191928
struct mlx5_ifc_qpc_bits {
19201929
u8 state[0x4];
1921-
u8 reserved_at_4[0x4];
1930+
u8 lag_tx_port_affinity[0x4];
19221931
u8 st[0x8];
19231932
u8 reserved_at_10[0x3];
19241933
u8 pm_state[0x2];
@@ -2167,7 +2176,11 @@ struct mlx5_ifc_traffic_counter_bits {
21672176
};
21682177

21692178
struct mlx5_ifc_tisc_bits {
2170-
u8 reserved_at_0[0xc];
2179+
u8 strict_lag_tx_port_affinity[0x1];
2180+
u8 reserved_at_1[0x3];
2181+
u8 lag_tx_port_affinity[0x04];
2182+
2183+
u8 reserved_at_8[0x4];
21712184
u8 prio[0x4];
21722185
u8 reserved_at_10[0x10];
21732186

@@ -4617,7 +4630,9 @@ struct mlx5_ifc_modify_tis_out_bits {
46174630
struct mlx5_ifc_modify_tis_bitmask_bits {
46184631
u8 reserved_at_0[0x20];
46194632

4620-
u8 reserved_at_20[0x1f];
4633+
u8 reserved_at_20[0x1d];
4634+
u8 lag_tx_port_affinity[0x1];
4635+
u8 strict_lag_tx_port_affinity[0x1];
46214636
u8 prio[0x1];
46224637
};
46234638

@@ -6215,7 +6230,10 @@ struct mlx5_ifc_create_flow_table_in_bits {
62156230
u8 reserved_at_e0[0x8];
62166231
u8 table_miss_id[0x18];
62176232

6218-
u8 reserved_at_100[0x100];
6233+
u8 reserved_at_100[0x8];
6234+
u8 lag_master_next_table_id[0x18];
6235+
6236+
u8 reserved_at_120[0x80];
62196237
};
62206238

62216239
struct mlx5_ifc_create_flow_group_out_bits {
@@ -7669,7 +7687,8 @@ struct mlx5_ifc_set_flow_table_root_in_bits {
76697687
};
76707688

76717689
enum {
7672-
MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7690+
MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7691+
MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
76737692
};
76747693

76757694
struct mlx5_ifc_modify_flow_table_out_bits {
@@ -7708,7 +7727,10 @@ struct mlx5_ifc_modify_flow_table_in_bits {
77087727
u8 reserved_at_e0[0x8];
77097728
u8 table_miss_id[0x18];
77107729

7711-
u8 reserved_at_100[0x100];
7730+
u8 reserved_at_100[0x8];
7731+
u8 lag_master_next_table_id[0x18];
7732+
7733+
u8 reserved_at_120[0x80];
77127734
};
77137735

77147736
struct mlx5_ifc_ets_tcn_config_reg_bits {
@@ -7816,4 +7838,134 @@ struct mlx5_ifc_dcbx_param_bits {
78167838
u8 error[0x8];
78177839
u8 reserved_at_a0[0x160];
78187840
};
7841+
7842+
struct mlx5_ifc_lagc_bits {
7843+
u8 reserved_at_0[0x1d];
7844+
u8 lag_state[0x3];
7845+
7846+
u8 reserved_at_20[0x14];
7847+
u8 tx_remap_affinity_2[0x4];
7848+
u8 reserved_at_38[0x4];
7849+
u8 tx_remap_affinity_1[0x4];
7850+
};
7851+
7852+
struct mlx5_ifc_create_lag_out_bits {
7853+
u8 status[0x8];
7854+
u8 reserved_at_8[0x18];
7855+
7856+
u8 syndrome[0x20];
7857+
7858+
u8 reserved_at_40[0x40];
7859+
};
7860+
7861+
struct mlx5_ifc_create_lag_in_bits {
7862+
u8 opcode[0x10];
7863+
u8 reserved_at_10[0x10];
7864+
7865+
u8 reserved_at_20[0x10];
7866+
u8 op_mod[0x10];
7867+
7868+
struct mlx5_ifc_lagc_bits ctx;
7869+
};
7870+
7871+
struct mlx5_ifc_modify_lag_out_bits {
7872+
u8 status[0x8];
7873+
u8 reserved_at_8[0x18];
7874+
7875+
u8 syndrome[0x20];
7876+
7877+
u8 reserved_at_40[0x40];
7878+
};
7879+
7880+
struct mlx5_ifc_modify_lag_in_bits {
7881+
u8 opcode[0x10];
7882+
u8 reserved_at_10[0x10];
7883+
7884+
u8 reserved_at_20[0x10];
7885+
u8 op_mod[0x10];
7886+
7887+
u8 reserved_at_40[0x20];
7888+
u8 field_select[0x20];
7889+
7890+
struct mlx5_ifc_lagc_bits ctx;
7891+
};
7892+
7893+
struct mlx5_ifc_query_lag_out_bits {
7894+
u8 status[0x8];
7895+
u8 reserved_at_8[0x18];
7896+
7897+
u8 syndrome[0x20];
7898+
7899+
u8 reserved_at_40[0x40];
7900+
7901+
struct mlx5_ifc_lagc_bits ctx;
7902+
};
7903+
7904+
struct mlx5_ifc_query_lag_in_bits {
7905+
u8 opcode[0x10];
7906+
u8 reserved_at_10[0x10];
7907+
7908+
u8 reserved_at_20[0x10];
7909+
u8 op_mod[0x10];
7910+
7911+
u8 reserved_at_40[0x40];
7912+
};
7913+
7914+
struct mlx5_ifc_destroy_lag_out_bits {
7915+
u8 status[0x8];
7916+
u8 reserved_at_8[0x18];
7917+
7918+
u8 syndrome[0x20];
7919+
7920+
u8 reserved_at_40[0x40];
7921+
};
7922+
7923+
struct mlx5_ifc_destroy_lag_in_bits {
7924+
u8 opcode[0x10];
7925+
u8 reserved_at_10[0x10];
7926+
7927+
u8 reserved_at_20[0x10];
7928+
u8 op_mod[0x10];
7929+
7930+
u8 reserved_at_40[0x40];
7931+
};
7932+
7933+
struct mlx5_ifc_create_vport_lag_out_bits {
7934+
u8 status[0x8];
7935+
u8 reserved_at_8[0x18];
7936+
7937+
u8 syndrome[0x20];
7938+
7939+
u8 reserved_at_40[0x40];
7940+
};
7941+
7942+
struct mlx5_ifc_create_vport_lag_in_bits {
7943+
u8 opcode[0x10];
7944+
u8 reserved_at_10[0x10];
7945+
7946+
u8 reserved_at_20[0x10];
7947+
u8 op_mod[0x10];
7948+
7949+
u8 reserved_at_40[0x40];
7950+
};
7951+
7952+
struct mlx5_ifc_destroy_vport_lag_out_bits {
7953+
u8 status[0x8];
7954+
u8 reserved_at_8[0x18];
7955+
7956+
u8 syndrome[0x20];
7957+
7958+
u8 reserved_at_40[0x40];
7959+
};
7960+
7961+
struct mlx5_ifc_destroy_vport_lag_in_bits {
7962+
u8 opcode[0x10];
7963+
u8 reserved_at_10[0x10];
7964+
7965+
u8 reserved_at_20[0x10];
7966+
u8 op_mod[0x10];
7967+
7968+
u8 reserved_at_40[0x40];
7969+
};
7970+
78197971
#endif /* MLX5_IFC_H */

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