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virtuosoIngo Molnar
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perf/x86/intel/pt: Factor out pt_config_start()
PT trace is now enabled at the bottom of the event configuration function that takes care of all configuration bits related to a given event, including the address filter update. This is only needed where the event configuration changes, that is, in ->add()/->start(). In the interrupt path we can use a lighter version that keeps the configuration intact, since it hasn't changed, and only flips the enable bit. Signed-off-by: Alexander Shishkin <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: David Ahern <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Cc: [email protected] Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
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  • arch/x86/events/intel

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arch/x86/events/intel/pt.c

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,20 @@ static bool pt_event_valid(struct perf_event *event)
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* These all are cpu affine and operate on a local PT
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*/
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400+
static void pt_config_start(struct perf_event *event)
401+
{
402+
struct pt *pt = this_cpu_ptr(&pt_ctx);
403+
u64 ctl = event->hw.config;
404+
405+
ctl |= RTIT_CTL_TRACEEN;
406+
if (READ_ONCE(pt->vmx_on))
407+
perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
408+
else
409+
wrmsrl(MSR_IA32_RTIT_CTL, ctl);
410+
411+
WRITE_ONCE(event->hw.config, ctl);
412+
}
413+
400414
/* Address ranges and their corresponding msr configuration registers */
401415
static const struct pt_address_range {
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unsigned long msr_a;
@@ -468,7 +482,6 @@ static u64 pt_config_filters(struct perf_event *event)
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static void pt_config(struct perf_event *event)
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{
471-
struct pt *pt = this_cpu_ptr(&pt_ctx);
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u64 reg;
473486

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/* First round: clear STATUS, in particular the PSB byte counter. */
@@ -501,10 +514,7 @@ static void pt_config(struct perf_event *event)
501514
reg |= (event->attr.config & PT_CONFIG_MASK);
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event->hw.config = reg;
504-
if (READ_ONCE(pt->vmx_on))
505-
perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
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else
507-
wrmsrl(MSR_IA32_RTIT_CTL, reg);
517+
pt_config_start(event);
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}
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static void pt_config_stop(struct perf_event *event)
@@ -1381,7 +1391,7 @@ void intel_pt_interrupt(void)
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pt_config_buffer(topa_to_page(buf->cur)->table, buf->cur_idx,
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buf->output_off);
1384-
pt_config(event);
1394+
pt_config_start(event);
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}
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}
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