@@ -397,6 +397,20 @@ static bool pt_event_valid(struct perf_event *event)
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* These all are cpu affine and operate on a local PT
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*/
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+ static void pt_config_start (struct perf_event * event )
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+ {
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+ struct pt * pt = this_cpu_ptr (& pt_ctx );
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+ u64 ctl = event -> hw .config ;
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+
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+ ctl |= RTIT_CTL_TRACEEN ;
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+ if (READ_ONCE (pt -> vmx_on ))
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+ perf_aux_output_flag (& pt -> handle , PERF_AUX_FLAG_PARTIAL );
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+ else
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+ wrmsrl (MSR_IA32_RTIT_CTL , ctl );
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+
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+ WRITE_ONCE (event -> hw .config , ctl );
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+ }
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+
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/* Address ranges and their corresponding msr configuration registers */
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static const struct pt_address_range {
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unsigned long msr_a ;
@@ -468,7 +482,6 @@ static u64 pt_config_filters(struct perf_event *event)
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static void pt_config (struct perf_event * event )
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{
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- struct pt * pt = this_cpu_ptr (& pt_ctx );
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u64 reg ;
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/* First round: clear STATUS, in particular the PSB byte counter. */
@@ -501,10 +514,7 @@ static void pt_config(struct perf_event *event)
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reg |= (event -> attr .config & PT_CONFIG_MASK );
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event -> hw .config = reg ;
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- if (READ_ONCE (pt -> vmx_on ))
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- perf_aux_output_flag (& pt -> handle , PERF_AUX_FLAG_PARTIAL );
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- else
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- wrmsrl (MSR_IA32_RTIT_CTL , reg );
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+ pt_config_start (event );
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}
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static void pt_config_stop (struct perf_event * event )
@@ -1381,7 +1391,7 @@ void intel_pt_interrupt(void)
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pt_config_buffer (topa_to_page (buf -> cur )-> table , buf -> cur_idx ,
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buf -> output_off );
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- pt_config (event );
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+ pt_config_start (event );
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}
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}
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