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Xiaofei Tandavem330
Xiaofei Tan
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davem330
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net: hns3: change print level of RAS error log from warning to error
This patch changes print level of RAS error log from warning to error. Because RAS error and its recovery process could cause application failure. Also uses %u instead of %d when the parameter is unsigned. Signed-off-by: Xiaofei Tan <[email protected]> Signed-off-by: Weihang Li <[email protected]> Signed-off-by: Huazhong Tan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -637,8 +637,8 @@ static void hclge_log_error(struct device *dev, char *reg,
637637
{
638638
while (err->msg) {
639639
if (err->int_msk & err_sts) {
640-
dev_warn(dev, "%s %s found [error status=0x%x]\n",
641-
reg, err->msg, err_sts);
640+
dev_err(dev, "%s %s found [error status=0x%x]\n",
641+
reg, err->msg, err_sts);
642642
if (err->reset_level &&
643643
err->reset_level != HNAE3_NONE_RESET)
644644
set_bit(err->reset_level, reset_requests);
@@ -1163,8 +1163,8 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
11631163

11641164
status = le32_to_cpu(*(desc_data + 3)) & BIT(0);
11651165
if (status) {
1166-
dev_warn(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",
1167-
status);
1166+
dev_err(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",
1167+
status);
11681168
set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
11691169
}
11701170

@@ -1200,8 +1200,8 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
12001200
desc_data = (__le32 *)&desc[5];
12011201
status = le32_to_cpu(*(desc_data + 1));
12021202
if (status) {
1203-
dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST1 %s found\n",
1204-
"rpu_rx_pkt_ecc_mbit_err");
1203+
dev_err(dev,
1204+
"PPU_MPF_ABNORMAL_INT_ST1 rpu_rx_pkt_ecc_mbit_err found\n");
12051205
set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
12061206
}
12071207

@@ -1379,17 +1379,17 @@ static int hclge_log_rocee_axi_error(struct hclge_dev *hdev)
13791379
return ret;
13801380
}
13811381

1382-
dev_info(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",
1383-
le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
1384-
le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
1385-
le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
1386-
dev_info(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",
1387-
le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]),
1388-
le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]),
1389-
le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5]));
1390-
dev_info(dev, "AXI3: %08X %08X %08X %08X\n",
1391-
le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]),
1392-
le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3]));
1382+
dev_err(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",
1383+
le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
1384+
le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
1385+
le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
1386+
dev_err(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",
1387+
le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]),
1388+
le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]),
1389+
le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5]));
1390+
dev_err(dev, "AXI3: %08X %08X %08X %08X\n",
1391+
le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]),
1392+
le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3]));
13931393

13941394
return 0;
13951395
}
@@ -1408,12 +1408,12 @@ static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev)
14081408
return ret;
14091409
}
14101410

1411-
dev_info(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",
1412-
le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
1413-
le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
1414-
le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
1415-
dev_info(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),
1416-
le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2]));
1411+
dev_err(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",
1412+
le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
1413+
le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
1414+
le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
1415+
dev_err(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),
1416+
le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2]));
14171417

14181418
return 0;
14191419
}
@@ -1442,23 +1442,23 @@ static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev)
14421442
le32_to_cpu(desc[0].data[0]);
14431443
while (err->msg) {
14441444
if (err->int_msk == err_sts) {
1445-
dev_warn(dev, "%s [error status=0x%x] found\n",
1446-
err->msg,
1447-
le32_to_cpu(desc[0].data[0]));
1445+
dev_err(dev, "%s [error status=0x%x] found\n",
1446+
err->msg,
1447+
le32_to_cpu(desc[0].data[0]));
14481448
break;
14491449
}
14501450
err++;
14511451
}
14521452
}
14531453

14541454
if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
1455-
dev_warn(dev, "ROCEE TSP OVF [error status=0x%x] found\n",
1456-
le32_to_cpu(desc[0].data[1]));
1455+
dev_err(dev, "ROCEE TSP OVF [error status=0x%x] found\n",
1456+
le32_to_cpu(desc[0].data[1]));
14571457
}
14581458

14591459
if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
1460-
dev_warn(dev, "ROCEE SCC OVF [error status=0x%x] found\n",
1461-
le32_to_cpu(desc[0].data[2]));
1460+
dev_err(dev, "ROCEE SCC OVF [error status=0x%x] found\n",
1461+
le32_to_cpu(desc[0].data[2]));
14621462
}
14631463

14641464
return 0;
@@ -1486,10 +1486,10 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
14861486

14871487
if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) {
14881488
if (status & HCLGE_ROCEE_RERR_INT_MASK)
1489-
dev_warn(dev, "ROCEE RAS AXI rresp error\n");
1489+
dev_err(dev, "ROCEE RAS AXI rresp error\n");
14901490

14911491
if (status & HCLGE_ROCEE_BERR_INT_MASK)
1492-
dev_warn(dev, "ROCEE RAS AXI bresp error\n");
1492+
dev_err(dev, "ROCEE RAS AXI bresp error\n");
14931493

14941494
reset_type = HNAE3_FUNC_RESET;
14951495

@@ -1499,7 +1499,7 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
14991499
}
15001500

15011501
if (status & HCLGE_ROCEE_ECC_INT_MASK) {
1502-
dev_warn(dev, "ROCEE RAS 2bit ECC error\n");
1502+
dev_err(dev, "ROCEE RAS 2bit ECC error\n");
15031503
reset_type = HNAE3_GLOBAL_RESET;
15041504

15051505
ret = hclge_log_rocee_ecc_error(hdev);
@@ -1640,16 +1640,16 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
16401640

16411641
/* Handling Non-fatal HNS RAS errors */
16421642
if (status & HCLGE_RAS_REG_NFE_MASK) {
1643-
dev_warn(dev,
1644-
"HNS Non-Fatal RAS error(status=0x%x) identified\n",
1645-
status);
1643+
dev_err(dev,
1644+
"HNS Non-Fatal RAS error(status=0x%x) identified\n",
1645+
status);
16461646
hclge_handle_all_ras_errors(hdev);
16471647
}
16481648

16491649
/* Handling Non-fatal Rocee RAS errors */
16501650
if (hdev->pdev->revision >= 0x21 &&
16511651
status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
1652-
dev_warn(dev, "ROCEE Non-Fatal RAS error identified\n");
1652+
dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");
16531653
hclge_handle_rocee_ras_error(ae_dev);
16541654
}
16551655

@@ -1728,8 +1728,8 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
17281728
return;
17291729
}
17301730

1731-
dev_warn(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%d), queue_id(%d)\n",
1732-
vf_id, q_id);
1731+
dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%u), queue_id(%u)\n",
1732+
vf_id, q_id);
17331733

17341734
if (vf_id) {
17351735
if (vf_id >= hdev->num_alloc_vport) {
@@ -1746,8 +1746,8 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
17461746

17471747
ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);
17481748
if (ret)
1749-
dev_warn(dev, "inform reset to vf(%d) failed %d!\n",
1750-
hdev->vport->vport_id, ret);
1749+
dev_err(dev, "inform reset to vf(%u) failed %d!\n",
1750+
hdev->vport->vport_id, ret);
17511751
} else {
17521752
set_bit(HNAE3_FUNC_RESET, reset_requests);
17531753
}
@@ -1793,8 +1793,8 @@ static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev,
17931793
status = le32_to_cpu(*(desc_data + 2)) &
17941794
HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
17951795
if (status)
1796-
dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",
1797-
status);
1796+
dev_err(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",
1797+
status);
17981798

17991799
/* clear all main PF MSIx errors */
18001800
ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);
@@ -1988,7 +1988,7 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
19881988

19891989
/* Handle Non-fatal HNS RAS errors */
19901990
if (status & HCLGE_RAS_REG_NFE_MASK) {
1991-
dev_warn(dev, "HNS hw error(RAS) identified during init\n");
1991+
dev_err(dev, "HNS hw error(RAS) identified during init\n");
19921992
hclge_handle_all_ras_errors(hdev);
19931993
}
19941994

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