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| 1 | +#define __ATOMIC_FETCH_OP_TEST(src_reg, dst_reg, operand1, op, operand2, expect) \ |
| 2 | + { \ |
| 3 | + "atomic fetch " #op ", src=" #dst_reg " dst=" #dst_reg, \ |
| 4 | + .insns = { \ |
| 5 | + /* u64 val = operan1; */ \ |
| 6 | + BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, operand1), \ |
| 7 | + /* u64 old = atomic_fetch_add(&val, operand2); */ \ |
| 8 | + BPF_MOV64_REG(dst_reg, BPF_REG_10), \ |
| 9 | + BPF_MOV64_IMM(src_reg, operand2), \ |
| 10 | + BPF_ATOMIC_OP(BPF_DW, op, \ |
| 11 | + dst_reg, src_reg, -8), \ |
| 12 | + /* if (old != operand1) exit(1); */ \ |
| 13 | + BPF_JMP_IMM(BPF_JEQ, src_reg, operand1, 2), \ |
| 14 | + BPF_MOV64_IMM(BPF_REG_0, 1), \ |
| 15 | + BPF_EXIT_INSN(), \ |
| 16 | + /* if (val != result) exit (2); */ \ |
| 17 | + BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -8), \ |
| 18 | + BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, expect, 2), \ |
| 19 | + BPF_MOV64_IMM(BPF_REG_0, 2), \ |
| 20 | + BPF_EXIT_INSN(), \ |
| 21 | + /* exit(0); */ \ |
| 22 | + BPF_MOV64_IMM(BPF_REG_0, 0), \ |
| 23 | + BPF_EXIT_INSN(), \ |
| 24 | + }, \ |
| 25 | + .result = ACCEPT, \ |
| 26 | + } |
| 27 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_2, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 28 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_0, BPF_REG_1, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 29 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_0, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 30 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_2, BPF_REG_3, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 31 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_4, BPF_REG_5, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 32 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_9, BPF_REG_8, 1, BPF_ADD | BPF_FETCH, 2, 3), |
| 33 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_2, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 34 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_0, BPF_REG_1, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 35 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_0, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 36 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_2, BPF_REG_3, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 37 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_4, BPF_REG_5, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 38 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_9, BPF_REG_8, 0x010, BPF_AND | BPF_FETCH, 0x011, 0x010), |
| 39 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_2, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 40 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_0, BPF_REG_1, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 41 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_0, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 42 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_2, BPF_REG_3, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 43 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_4, BPF_REG_5, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 44 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_9, BPF_REG_8, 0x010, BPF_OR | BPF_FETCH, 0x011, 0x011), |
| 45 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_2, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 46 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_0, BPF_REG_1, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 47 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_0, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 48 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_2, BPF_REG_3, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 49 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_4, BPF_REG_5, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 50 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_9, BPF_REG_8, 0x010, BPF_XOR | BPF_FETCH, 0x011, 0x001), |
| 51 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_2, 0x010, BPF_XCHG, 0x011, 0x011), |
| 52 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_0, BPF_REG_1, 0x010, BPF_XCHG, 0x011, 0x011), |
| 53 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_1, BPF_REG_0, 0x010, BPF_XCHG, 0x011, 0x011), |
| 54 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_2, BPF_REG_3, 0x010, BPF_XCHG, 0x011, 0x011), |
| 55 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_4, BPF_REG_5, 0x010, BPF_XCHG, 0x011, 0x011), |
| 56 | +__ATOMIC_FETCH_OP_TEST(BPF_REG_9, BPF_REG_8, 0x010, BPF_XCHG, 0x011, 0x011), |
| 57 | +#undef __ATOMIC_FETCH_OP_TEST |
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