ARM: dts: fix L2 address in Hi3620

Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: Haojian Zhuang <[email protected]>
Acked-by: Wei Xu <[email protected]>
Cc: [email protected]
Signed-off-by: Arnd Bergmann <[email protected]>

Author: hzhuang1

arch/arm/boot/dts/hi3620.dtsi

@@ -73,7 +73,7 @@
 
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
-			reg = <0xfc10000 0x100000>;
+			reg = <0x100000 0x100000>;
 			interrupts = <0 15 4>;
 			cache-unified;
 			cache-level = <2>;