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[LoongArch] Permit auto-vectorization using LSX/LASX with auto-vec feature (llvm#78943)
With enough codegen complete, we can now correctly report the size of vector registers for LSX/LASX, allowing auto vectorization (The `auto-vec` feature needs to be enabled simultaneously). As described, the `auto-vec` feature is an experimental one. To ensure that automatic vectorization is not enabled by default, because the information provided by the current `TTI` cannot yield additional benefits for automatic vectorization.
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‎llvm/lib/Target/LoongArch/LoongArch.td

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@@ -106,6 +106,11 @@ def FeatureRelax
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: SubtargetFeature<"relax", "HasLinkerRelax", "true",
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"Enable Linker relaxation">;
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// Experimental auto vectorization
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def FeatureAutoVec
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: SubtargetFeature<"auto-vec", "HasExpAutoVec", "true",
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"Experimental auto vectorization">;
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//===----------------------------------------------------------------------===//
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// Registers, instruction descriptions ...
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/LoongArch/LoongArchSubtarget.h

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@@ -44,6 +44,7 @@ class LoongArchSubtarget : public LoongArchGenSubtargetInfo {
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bool HasLaLocalWithAbs = false;
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bool HasUAL = false;
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bool HasLinkerRelax = false;
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bool HasExpAutoVec = false;
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unsigned GRLen = 32;
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MVT GRLenVT = MVT::i32;
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LoongArchABI::ABI TargetABI = LoongArchABI::ABI_Unknown;
@@ -102,6 +103,7 @@ class LoongArchSubtarget : public LoongArchGenSubtargetInfo {
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bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; }
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bool hasUAL() const { return HasUAL; }
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bool hasLinkerRelax() const { return HasLinkerRelax; }
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bool hasExpAutoVec() const { return HasExpAutoVec; }
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MVT getGRLenVT() const { return GRLenVT; }
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unsigned getGRLen() const { return GRLen; }
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LoongArchABI::ABI getTargetABI() const { return TargetABI; }

‎llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp

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@@ -19,4 +19,22 @@ using namespace llvm;
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#define DEBUG_TYPE "loongarchtti"
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TypeSize LoongArchTTIImpl::getRegisterBitWidth(
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TargetTransformInfo::RegisterKind K) const {
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
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case TargetTransformInfo::RGK_FixedWidthVector:
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if (ST->hasExtLASX() && ST->hasExpAutoVec())
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return TypeSize::getFixed(256);
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if (ST->hasExtLSX() && ST->hasExpAutoVec())
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return TypeSize::getFixed(128);
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return TypeSize::getFixed(0);
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case TargetTransformInfo::RGK_ScalableVector:
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return TypeSize::getScalable(0);
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}
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llvm_unreachable("Unsupported register kind");
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}
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// TODO: Implement more hooks to provide TTI machinery for LoongArch.

‎llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h

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@@ -39,6 +39,8 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
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// TODO: Implement more hooks to provide TTI machinery for LoongArch.
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};
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‎llvm/test/Transforms/LoopVectorize/LoongArch/defaults.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt < %s -passes=loop-vectorize -mtriple loongarch64-linux-gnu -mattr=+lasx,+auto-vec -S | FileCheck %s
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;; This is a collection of tests whose only purpose is to show changes in the
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;; default configuration. Please keep these tests minimal - if you're testing
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;; functionality of some specific configuration, please place that in a
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;; seperate test file with a hard coded configuration (even if that
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;; configuration is the current default).
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "loongarch64"
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define void @vector_add(ptr noalias nocapture %a, i64 %v) {
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; CHECK-LABEL: define void @vector_add(
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; CHECK-SAME: ptr noalias nocapture [[A:%.*]], i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[V]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8
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; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr [[TMP2]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1024, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
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; CHECK-NEXT: [[ELEM:%.*]] = load i64, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ELEM]], [[V]]
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; CHECK-NEXT: store i64 [[ADD]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
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%elem = load i64, ptr %arrayidx
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%add = add i64 %elem, %v
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store i64 %add, ptr %arrayidx
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, 1024
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end:
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ret void
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}

‎llvm/test/Transforms/LoopVectorize/LoongArch/lit.local.cfg

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config.suffixes = [".ll"]
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if not "LoongArch" in config.root.targets:
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config.unsupported = True

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