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Merge pull request ARMmbed#50 from linlingao/spi_port
Add the 1st draft of SPI HAL driver. Fix more compiler warnings.
2 parents 99d6ce3 + 1ca3235 commit c4e3923

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9 files changed

+573
-16
lines changed

9 files changed

+573
-16
lines changed

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PinNames.h

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@@ -121,6 +121,18 @@ typedef enum {
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BUTTON1 = PIN_04,
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BUTTON2 = PIN_15,
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//SPI1
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SPICC32XXDMA_MOSI = P07,
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SPICC32XXDMA_MISO = P06,
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SPICC32XXDMA_CLK = P05,
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SPICC32XXDMA_CS = P08,
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// CI Shield
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D10 = SPICC32XXDMA_CS,
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D11 = SPICC32XXDMA_MOSI,
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D12 = SPICC32XXDMA_MISO,
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D13 = SPICC32XXDMA_CLK,
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// Not connected
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NC = (int)0xFFFFFFFF,
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PIN_RESERVED = NC,

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_LAUNCHXL.c

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@@ -68,16 +68,6 @@ const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
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*/
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void CC3220SF_LAUNCHXL_initGeneral(void)
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{
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PRCMPeripheralReset(PRCM_TIMERA0);
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PRCMPeripheralReset(PRCM_TIMERA1);
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PRCMPeripheralReset(PRCM_TIMERA2);
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PRCMPeripheralReset(PRCM_TIMERA3);
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PRCMPeripheralReset(PRCM_UARTA0);
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PRCMPeripheralReset(PRCM_UARTA1);
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PRCMPeripheralReset(PRCM_GPIOA0);
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PRCMPeripheralReset(PRCM_GPIOA1);
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PRCMPeripheralReset(PRCM_GPIOA2);
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PRCMPeripheralReset(PRCM_GPIOA3);
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MAP_IntMasterEnable();
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//MAP_IntEnable(FAULT_SYSTICK);
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PRCMCC3200MCUInit();

targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h

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@@ -16,6 +16,7 @@
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#ifndef MBED_OBJECTS_H
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#define MBED_OBJECTS_H
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#include "stdbool.h"
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#include "cmsis.h"
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#include "PortNames.h"
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#include "PeripheralNames.h"
@@ -60,6 +61,94 @@ struct serial_s {
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UART_PAR parityType; /* Parity bit type for UART */
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};
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typedef struct spi_clock_config_s {
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//! \param ulSPIClk is the rate of clock supplied to the SPI module.
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uint32_t ulSPIClk;
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//! \param ulBitRate is the desired bit rate.(master mode)
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uint32_t ulBitRate;
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//!
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//! The SPI module can operate in either master or slave mode. The parameter
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//! \e ulMode can be one of the following
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//! -\b SPI_MODE_MASTER
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//! -\b SPI_MODE_SLAVE
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uint32_t ulMode;
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//!
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//! The SPI module supports 4 sub modes based on SPI clock polarity and phase.
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//!
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//! <pre>
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//! Polarity Phase Sub-Mode
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//! 0 0 0
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//! 0 1 1
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//! 1 0 2
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//! 1 1 3
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//! </pre>
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//! Required sub mode can be select by setting \e ulSubMode parameter to one
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//! of the following
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//! - \b SPI_SUB_MODE_0
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//! - \b SPI_SUB_MODE_1
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//! - \b SPI_SUB_MODE_2
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//! - \b SPI_SUB_MODE_3
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uint32_t ulSubMode;
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//! The parameter \e ulConfig is logical OR of five values: the word length,
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//! active level for chip select, software or hardware controlled chip select,
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//! 3 or 4 pin mode and turbo mode.
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//! mode.
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//!
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//! SPI support 8, 16 and 32 bit word lengths defined by:-
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//! - \b SPI_WL_8
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//! - \b SPI_WL_16
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//! - \b SPI_WL_32
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//!
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//! Active state of Chip Select can be defined by:-
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//! - \b SPI_CS_ACTIVELOW
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//! - \b SPI_CS_ACTIVEHIGH
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//!
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//! SPI chip select can be configured to be controlled either by hardware or
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//! software:-
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//! - \b SPI_SW_CS
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//! - \b SPI_HW_CS
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//!
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//! The module can work in 3 or 4 pin mode defined by:-
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//! - \b SPI_3PIN_MODE
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//! - \b SPI_4PIN_MODE
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//!
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//! Turbo mode can be set on or turned off using:-
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//! - \b SPI_TURBO_MODE_ON
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//! - \b SPI_TURBO_MODE_OFF
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uint32_t ulConfig;
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} spi_clock_config_t;
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struct spi_s {
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/*! SPI module number */
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uint32_t instance;
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/*! SPICC32XXDMA Peripheral's base address */
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uint32_t baseAddr;
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/*! SPI Word lengh */
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uint32_t word_length;
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/*! SPI clock configuration */
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spi_clock_config_t clock_config;
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/*! Is clock update needed */
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bool clock_update;
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/*! Is CS controlled by GPIO */
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bool cs_control_gpio;
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#if DEVICE_SPI_ASYNCH
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uint32_t handler;
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uint32_t mask;
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uint32_t event;
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#endif
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};
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#ifdef __cplusplus
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}
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#endif

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