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58 | 58 | #include <ti/devices/cc32xx/driverlib/interrupt.h>
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59 | 59 | #include <ti/devices/cc32xx/driverlib/wdt.h>
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60 | 60 |
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| 61 | +#include <ti/drivers/Power.h> |
| 62 | +#include <ti/drivers/power/PowerCC32XX.h> |
| 63 | + |
61 | 64 | #include "CC3220SF_LAUNCHXL.h"
|
| 65 | + |
| 66 | +/* |
| 67 | + * =============================== Power =============================== |
| 68 | + */ |
| 69 | +/* |
| 70 | + * This table defines the parking state to be set for each parkable pin |
| 71 | + * during LPDS. (Device pins must be parked during LPDS to achieve maximum |
| 72 | + * power savings.) If the pin should be left unparked, specify the state |
| 73 | + * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device |
| 74 | + * will automatically park the pin in a high state during transition to LPDS, |
| 75 | + * so the Power Manager does not need to explictly park the pin. So the |
| 76 | + * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. |
| 77 | + */ |
| 78 | +PowerCC32XX_ParkInfo parkInfo[] = { |
| 79 | +/* PIN PARK STATE PIN ALIAS (FUNCTION) |
| 80 | + ----------------- ------------------------------ -------------------- */ |
| 81 | + {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ |
| 82 | + {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ |
| 83 | + {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ |
| 84 | + {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ |
| 85 | + {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ |
| 86 | + {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ |
| 87 | + {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ |
| 88 | + {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ |
| 89 | + {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ |
| 90 | + {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ |
| 91 | + {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ |
| 92 | + {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ |
| 93 | + {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ |
| 94 | + {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ |
| 95 | + {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ |
| 96 | + {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ |
| 97 | + {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ |
| 98 | + {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ |
| 99 | + {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ |
| 100 | + {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ |
| 101 | + {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ |
| 102 | + {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ |
| 103 | + {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */ |
| 104 | + {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */ |
| 105 | + {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ |
| 106 | + {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ |
| 107 | + {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ |
| 108 | + {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ |
| 109 | + {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ |
| 110 | + {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ |
| 111 | + {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ |
| 112 | +}; |
| 113 | + |
| 114 | +/* |
| 115 | + * This structure defines the configuration for the Power Manager. |
| 116 | + * |
| 117 | + * In this configuration the Power policy is disabled by default (because |
| 118 | + * enablePolicy is set to false). The Power policy can be enabled dynamically |
| 119 | + * at runtime by calling Power_enablePolicy(), or at build time, by changing |
| 120 | + * enablePolicy to true in this structure. |
| 121 | + */ |
| 122 | +const PowerCC32XX_ConfigV1 PowerCC32XX_config = { |
| 123 | + .policyInitFxn = &PowerCC32XX_initPolicy, |
| 124 | + .policyFxn = &PowerCC32XX_sleepPolicy, |
| 125 | + .enterLPDSHookFxn = NULL, |
| 126 | + .resumeLPDSHookFxn = NULL, |
| 127 | + .enablePolicy = false, |
| 128 | + .enableGPIOWakeupLPDS = true, |
| 129 | + .enableGPIOWakeupShutdown = true, |
| 130 | + .enableNetworkWakeupLPDS = true, |
| 131 | + .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, |
| 132 | + .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, |
| 133 | + .wakeupGPIOFxnLPDS = NULL, |
| 134 | + .wakeupGPIOFxnLPDSArg = 0, |
| 135 | + .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13, |
| 136 | + .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE, |
| 137 | + .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | |
| 138 | + PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, |
| 139 | + .keepDebugActiveDuringLPDS = false, |
| 140 | + .ioRetentionShutdown = PRCM_IO_RET_GRP_1, |
| 141 | + .pinParkDefs = parkInfo, |
| 142 | + .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) |
| 143 | +}; |
62 | 144 | /*
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63 | 145 | * =============================== SPI ===============================
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64 | 146 | */
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@@ -186,6 +268,7 @@ void CC3220SF_LAUNCHXL_initGeneral(void)
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186 | 268 | MAP_IntMasterEnable();
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187 | 269 | //MAP_IntEnable(FAULT_SYSTICK);
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188 | 270 | PRCMCC3200MCUInit();
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| 271 | + //Power_init(); |
189 | 272 | }
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190 | 273 |
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191 | 274 | #define __SF_DEBUG__
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