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DanielmachonPaolo Abeni
Danielmachon
authored and
Paolo Abeni
committed
net: sparx5: add is_sparx5 macro and use it throughout
We dont want to ops out each time a function needs to do some platform specifics. In particular we have a few places, where it would be convenient to just branch out on the platform type. Add the function is_sparx5() and, initially, use it for: - register writes that should only be done on Sparx5 (QSYS_CAL_CTRL, CLKGEN_LCPLL1_CORE_CLK). - function calls that should only be done on Sparx5 (ethtool_op_get_ts_info()) - register writes that are chip-exclusive (MASK_CFG1/2, PGID_CFG1/2, these are replicated for n_ports >32 on Sparx5). The is_sparx5() function simply checks the target chip type, to determine if this is a Sparx5 SKU or not. Reviewed-by: Steen Hegelund <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Signed-off-by: Daniel Machon <[email protected]> Signed-off-by: Paolo Abeni <[email protected]>
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‎drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -194,9 +194,10 @@ int sparx5_config_auto_calendar(struct sparx5 *sparx5)
194194
}
195195

196196
/* Halt the calendar while changing it */
197-
spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
198-
QSYS_CAL_CTRL_CAL_MODE,
199-
sparx5, QSYS_CAL_CTRL);
197+
if (is_sparx5(sparx5))
198+
spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
199+
QSYS_CAL_CTRL_CAL_MODE,
200+
sparx5, QSYS_CAL_CTRL);
200201

201202
/* Assign port bandwidth to auto calendar */
202203
for (idx = 0; idx < consts->n_auto_cals; idx++)

‎drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1189,7 +1189,7 @@ static int sparx5_get_ts_info(struct net_device *dev,
11891189
struct sparx5 *sparx5 = port->sparx5;
11901190
struct sparx5_phc *phc;
11911191

1192-
if (!sparx5->ptp)
1192+
if (!sparx5->ptp && is_sparx5(sparx5))
11931193
return ethtool_op_get_ts_info(dev, info);
11941194

11951195
phc = &sparx5->phc[SPARX5_PHC_PORT];

‎drivers/net/ethernet/microchip/sparx5/sparx5_main.c

Lines changed: 54 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -208,6 +208,25 @@ static const struct sparx5_main_io_resource sparx5_main_iomap[] = {
208208
{ TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */
209209
};
210210

211+
bool is_sparx5(struct sparx5 *sparx5)
212+
{
213+
switch (sparx5->target_ct) {
214+
case SPX5_TARGET_CT_7546:
215+
case SPX5_TARGET_CT_7549:
216+
case SPX5_TARGET_CT_7552:
217+
case SPX5_TARGET_CT_7556:
218+
case SPX5_TARGET_CT_7558:
219+
case SPX5_TARGET_CT_7546TSN:
220+
case SPX5_TARGET_CT_7549TSN:
221+
case SPX5_TARGET_CT_7552TSN:
222+
case SPX5_TARGET_CT_7556TSN:
223+
case SPX5_TARGET_CT_7558TSN:
224+
return true;
225+
default:
226+
return false;
227+
}
228+
}
229+
211230
static int sparx5_create_targets(struct sparx5 *sparx5)
212231
{
213232
const struct sparx5_main_io_resource *iomap = sparx5->data->iomap;
@@ -462,44 +481,45 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5)
462481
return -ENODEV;
463482
}
464483

465-
switch (freq) {
466-
case SPX5_CORE_CLOCK_250MHZ:
467-
clk_div = 10;
468-
pol_upd_int = 312;
469-
break;
470-
case SPX5_CORE_CLOCK_500MHZ:
471-
clk_div = 5;
472-
pol_upd_int = 624;
473-
break;
474-
case SPX5_CORE_CLOCK_625MHZ:
475-
clk_div = 4;
476-
pol_upd_int = 780;
477-
break;
478-
default:
479-
dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n",
480-
sparx5->coreclock, sparx5->target_ct);
481-
return -EINVAL;
484+
if (is_sparx5(sparx5)) {
485+
switch (freq) {
486+
case SPX5_CORE_CLOCK_250MHZ:
487+
clk_div = 10;
488+
pol_upd_int = 312;
489+
break;
490+
case SPX5_CORE_CLOCK_500MHZ:
491+
clk_div = 5;
492+
pol_upd_int = 624;
493+
break;
494+
case SPX5_CORE_CLOCK_625MHZ:
495+
clk_div = 4;
496+
pol_upd_int = 780;
497+
break;
498+
default:
499+
dev_err(sparx5->dev,
500+
"%d coreclock not supported on (%#04x)\n",
501+
sparx5->coreclock, sparx5->target_ct);
502+
return -EINVAL;
503+
}
504+
505+
/* Configure the LCPLL */
506+
spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
507+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
508+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
509+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
510+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
511+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
512+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
513+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
514+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
515+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
516+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
517+
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
518+
sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG);
482519
}
483520

484521
/* Update state with chosen frequency */
485522
sparx5->coreclock = freq;
486-
487-
/* Configure the LCPLL */
488-
spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
489-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
490-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
491-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
492-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
493-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
494-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
495-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
496-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
497-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
498-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
499-
CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
500-
sparx5,
501-
CLKGEN_LCPLL1_CORE_CLK_CFG);
502-
503523
clk_period = sparx5_clk_period(freq);
504524

505525
spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),

‎drivers/net/ethernet/microchip/sparx5/sparx5_main.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,6 +376,9 @@ struct sparx5 {
376376
const struct sparx5_match_data *data;
377377
};
378378

379+
/* sparx5_main.c */
380+
bool is_sparx5(struct sparx5 *sparx5);
381+
379382
/* sparx5_switchdev.c */
380383
int sparx5_register_notifier_blocks(struct sparx5 *sparx5);
381384
void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5);

‎drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c

Lines changed: 28 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,10 @@ static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid)
1616

1717
/* Output mask to respective registers */
1818
spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid));
19-
spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid));
20-
spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid));
19+
if (is_sparx5(sparx5)) {
20+
spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid));
21+
spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid));
22+
}
2123

2224
return 0;
2325
}
@@ -141,15 +143,19 @@ void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable)
141143
void sparx5_pgid_clear(struct sparx5 *spx5, int pgid)
142144
{
143145
spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid));
144-
spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid));
145-
spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid));
146+
if (is_sparx5(spx5)) {
147+
spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid));
148+
spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid));
149+
}
146150
}
147151

148152
void sparx5_pgid_read_mask(struct sparx5 *spx5, int pgid, u32 portmask[3])
149153
{
150154
portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid));
151-
portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid));
152-
portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid));
155+
if (is_sparx5(spx5)) {
156+
portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid));
157+
portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid));
158+
}
153159
}
154160

155161
void sparx5_update_fwd(struct sparx5 *sparx5)
@@ -164,8 +170,10 @@ void sparx5_update_fwd(struct sparx5 *sparx5)
164170
/* Update flood masks */
165171
for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) {
166172
spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port));
167-
spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));
168-
spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));
173+
if (is_sparx5(sparx5)) {
174+
spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));
175+
spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));
176+
}
169177
}
170178

171179
/* Update SRC masks */
@@ -176,12 +184,16 @@ void sparx5_update_fwd(struct sparx5 *sparx5)
176184
clear_bit(port, workmask);
177185
bitmap_to_arr32(mask, workmask, SPX5_PORTS);
178186
spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port));
179-
spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));
180-
spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));
187+
if (is_sparx5(sparx5)) {
188+
spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));
189+
spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));
190+
}
181191
} else {
182192
spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port));
183-
spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port));
184-
spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port));
193+
if (is_sparx5(sparx5)) {
194+
spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port));
195+
spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port));
196+
}
185197
}
186198
}
187199

@@ -192,8 +204,10 @@ void sparx5_update_fwd(struct sparx5 *sparx5)
192204

193205
/* Apply learning mask */
194206
spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG);
195-
spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1);
196-
spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2);
207+
if (is_sparx5(sparx5)) {
208+
spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1);
209+
spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2);
210+
}
197211
}
198212

199213
void sparx5_vlan_port_apply(struct sparx5 *sparx5,

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