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Rafal Ostrowskialexdeucher
Rafal Ostrowski
authored and
alexdeucher
committed
drm/amd/display: DML2.1 Post-Si Cleanup
[Why] There are a few cleanup and refactoring tasks that need to be done with the DML2.1 wrapper and DC interface to remove dependencies on legacy structures and N-1 prototypes. [How] Implemented pipe_ctx->global_sync. Implemented new functions to use pipe_ctx->hubp_regs and pipe_ctx->global_sync: - hubp_setup2 - hubp_setup_interdependent2 - Several other new functions for DCN 4.01 to support newer structures Removed dml21_update_pipe_ctx_dchub_regs Removed dml21_extract_legacy_watermark_set Removed dml21_populate_pipe_ctx_dlg_param Removed outdated dcn references in DML2.1 wrapper. Reviewed-by: Austin Zheng <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Rafal Ostrowski <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent 00d53a0 commit 63ab80d

38 files changed

+1077
-810
lines changed

‎drivers/gpu/drm/amd/display/dc/core/dc_resource.c

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4478,7 +4478,7 @@ static void set_hfvs_info_packet(
44784478
static void adaptive_sync_override_dp_info_packets_sdp_line_num(
44794479
const struct dc_crtc_timing *timing,
44804480
struct enc_sdp_line_num *sdp_line_num,
4481-
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4481+
unsigned int vstartup_start)
44824482
{
44834483
uint32_t asic_blank_start = 0;
44844484
uint32_t asic_blank_end = 0;
@@ -4493,8 +4493,8 @@ static void adaptive_sync_override_dp_info_packets_sdp_line_num(
44934493
asic_blank_end = (asic_blank_start - tg->v_border_bottom -
44944494
tg->v_addressable - tg->v_border_top);
44954495

4496-
if (pipe_dlg_param->vstartup_start > asic_blank_end) {
4497-
v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));
4496+
if (vstartup_start > asic_blank_end) {
4497+
v_update = (tg->v_total - (vstartup_start - asic_blank_end));
44984498
sdp_line_num->adaptive_sync_line_num_valid = true;
44994499
sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);
45004500
} else {
@@ -4507,15 +4507,15 @@ static void set_adaptive_sync_info_packet(
45074507
struct dc_info_packet *info_packet,
45084508
const struct dc_stream_state *stream,
45094509
struct encoder_info_frame *info_frame,
4510-
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
4510+
unsigned int vstartup_start)
45114511
{
45124512
if (!stream->adaptive_sync_infopacket.valid)
45134513
return;
45144514

45154515
adaptive_sync_override_dp_info_packets_sdp_line_num(
45164516
&stream->timing,
45174517
&info_frame->sdp_line_num,
4518-
pipe_dlg_param);
4518+
vstartup_start);
45194519

45204520
*info_packet = stream->adaptive_sync_infopacket;
45214521
}
@@ -4548,6 +4548,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
45484548
{
45494549
enum signal_type signal = SIGNAL_TYPE_NONE;
45504550
struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
4551+
unsigned int vstartup_start = 0;
45514552

45524553
/* default all packets to invalid */
45534554
info->avi.valid = false;
@@ -4561,6 +4562,9 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
45614562
info->adaptive_sync.valid = false;
45624563
signal = pipe_ctx->stream->signal;
45634564

4565+
if (pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe)
4566+
vstartup_start = pipe_ctx->stream->ctx->dc->res_pool->funcs->get_vstartup_for_pipe(pipe_ctx);
4567+
45644568
/* HDMi and DP have different info packets*/
45654569
if (dc_is_hdmi_signal(signal)) {
45664570
set_avi_info_frame(&info->avi, pipe_ctx);
@@ -4582,7 +4586,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
45824586
set_adaptive_sync_info_packet(&info->adaptive_sync,
45834587
pipe_ctx->stream,
45844588
info,
4585-
&pipe_ctx->pipe_dlg_param);
4589+
vstartup_start);
45864590
}
45874591

45884592
patch_gamut_packet_checksum(&info->gamut);

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

Lines changed: 0 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@
1010
#include "dml21_utils.h"
1111
#include "dml21_translation_helper.h"
1212
#include "bounding_boxes/dcn4_soc_bb.h"
13-
#include "bounding_boxes/dcn3_soc_bb.h"
1413

1514
static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_init,
1615
const struct dml2_configuration_options *config,
@@ -20,10 +19,6 @@ static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_
2019
const struct dml2_soc_qos_parameters *qos_params;
2120

2221
switch (in_dc->ctx->dce_version) {
23-
case DCN_VERSION_3_2: // TODO : Temporary for N-1 validation. Remove this after N-1 validation phase is complete.
24-
soc_bb = &dml2_socbb_dcn31;
25-
qos_params = &dml_dcn31_soc_qos_params;
26-
break;
2722
case DCN_VERSION_4_01:
2823
default:
2924
if (config->bb_from_dmub)
@@ -60,9 +55,6 @@ static void dml21_init_ip_params(struct dml2_initialize_instance_in_out *dml_ini
6055
const struct dml2_ip_capabilities *ip_caps;
6156

6257
switch (in_dc->ctx->dce_version) {
63-
case DCN_VERSION_3_2: // TODO : Temporary for N-1 validation. Remove this after N-1 validation phase is complete.
64-
ip_caps = &dml2_dcn31_max_ip_caps;
65-
break;
6658
case DCN_VERSION_4_01:
6759
default:
6860
ip_caps = &dml2_dcn401_max_ip_caps;
@@ -1091,28 +1083,6 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
10911083
context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;
10921084
}
10931085

1094-
void dml21_extract_legacy_watermark_set(const struct dc *in_dc, struct dcn_watermarks *watermark, enum dml2_dchub_watermark_reg_set_index reg_set_idx, struct dml2_context *in_ctx)
1095-
{
1096-
struct dml2_core_internal_display_mode_lib *mode_lib = &in_ctx->v21.dml_init.dml2_instance->core_instance.clean_me_up.mode_lib;
1097-
double refclk_freq_in_mhz = (in_ctx->v21.display_config.overrides.hw.dlg_ref_clk_mhz > 0) ? (double)in_ctx->v21.display_config.overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz;
1098-
1099-
if (reg_set_idx >= DML2_DCHUB_WATERMARK_SET_NUM) {
1100-
/* invalid register set index */
1101-
return;
1102-
}
1103-
1104-
/* convert to legacy format (time in ns) */
1105-
watermark->urgent_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;
1106-
watermark->pte_meta_urgent_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;
1107-
watermark->cstate_pstate.cstate_enter_plus_exit_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].sr_enter / refclk_freq_in_mhz) * 1000.0;
1108-
watermark->cstate_pstate.cstate_exit_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].sr_exit / refclk_freq_in_mhz) * 1000.0;
1109-
watermark->cstate_pstate.pstate_change_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].uclk_pstate / refclk_freq_in_mhz) * 1000.0;
1110-
watermark->urgent_latency_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].urgent / refclk_freq_in_mhz) * 1000.0;
1111-
watermark->cstate_pstate.fclk_pstate_change_ns = ((double)in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].fclk_pstate / refclk_freq_in_mhz) * 1000.0;
1112-
watermark->frac_urg_bw_flip = in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].frac_urg_bw_flip;
1113-
watermark->frac_urg_bw_nom = in_ctx->v21.mode_programming.programming->global_regs.wm_regs[reg_set_idx].frac_urg_bw_nom;
1114-
}
1115-
11161086
static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)
11171087
{
11181088
struct dml2_dchub_watermark_regs *wm_regs = NULL;
@@ -1156,53 +1126,6 @@ void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_se
11561126
}
11571127
}
11581128

1159-
1160-
void dml21_populate_pipe_ctx_dlg_params(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming)
1161-
{
1162-
unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end;
1163-
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1164-
union dml2_global_sync_programming *global_sync = &stream_programming->global_sync;
1165-
1166-
hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right + pipe_ctx->hblank_borrow;
1167-
vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top;
1168-
hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch;
1169-
vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch;
1170-
1171-
hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right - pipe_ctx->hblank_borrow;
1172-
vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom;
1173-
1174-
if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
1175-
/* phantom has its own global sync */
1176-
global_sync = &stream_programming->phantom_stream.global_sync;
1177-
}
1178-
1179-
pipe_ctx->pipe_dlg_param.vstartup_start = global_sync->dcn4x.vstartup_lines;
1180-
pipe_ctx->pipe_dlg_param.vupdate_offset = global_sync->dcn4x.vupdate_offset_pixels;
1181-
pipe_ctx->pipe_dlg_param.vupdate_width = global_sync->dcn4x.vupdate_vupdate_width_pixels;
1182-
pipe_ctx->pipe_dlg_param.vready_offset = global_sync->dcn4x.vready_offset_pixels;
1183-
pipe_ctx->pipe_dlg_param.pstate_keepout = global_sync->dcn4x.pstate_keepout_start_lines;
1184-
1185-
pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst;
1186-
1187-
pipe_ctx->pipe_dlg_param.hactive = hactive;
1188-
pipe_ctx->pipe_dlg_param.vactive = vactive;
1189-
pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total;
1190-
pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total;
1191-
pipe_ctx->pipe_dlg_param.hblank_end = hblank_end;
1192-
pipe_ctx->pipe_dlg_param.vblank_end = vblank_end;
1193-
pipe_ctx->pipe_dlg_param.hblank_start = hblank_start;
1194-
pipe_ctx->pipe_dlg_param.vblank_start = vblank_start;
1195-
pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch;
1196-
pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;
1197-
pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;
1198-
pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max;
1199-
pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min;
1200-
pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height;
1201-
pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width;
1202-
pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height;
1203-
pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width;
1204-
}
1205-
12061129
void dml21_map_hw_resources(struct dml2_context *dml_ctx)
12071130
{
12081131
unsigned int i = 0;

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,6 @@ void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_
2121
void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);
2222
bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
2323
void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);
24-
void dml21_populate_pipe_ctx_dlg_params(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming);
25-
void dml21_extract_legacy_watermark_set(const struct dc *in_dc, struct dcn_watermarks *watermark, enum dml2_dchub_watermark_reg_set_index reg_set_idx, struct dml2_context *in_ctx);
2624
void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);
2725
void dml21_map_hw_resources(struct dml2_context *dml_ctx);
2826
void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_utils.c

Lines changed: 15 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -142,108 +142,21 @@ int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,
142142
return num_pipes;
143143
}
144144

145-
146-
void dml21_update_pipe_ctx_dchub_regs(struct dml2_display_rq_regs *rq_regs,
147-
struct dml2_display_dlg_regs *disp_dlg_regs,
148-
struct dml2_display_ttu_regs *disp_ttu_regs,
149-
struct pipe_ctx *out)
145+
void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx,
146+
struct dc_state *context,
147+
struct pipe_ctx *pipe_ctx,
148+
struct dml2_per_stream_programming *stream_programming)
150149
{
151-
memset(&out->rq_regs, 0, sizeof(out->rq_regs));
152-
out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;
153-
out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;
154-
//out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;
155-
//out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;
156-
out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;
157-
out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;
158-
out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;
159-
out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;
160-
161-
out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;
162-
out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;
163-
//out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;
164-
//out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;
165-
out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;
166-
out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;
167-
out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;
168-
out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;
169-
170-
out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;
171-
out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;
172-
//out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;
173-
out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;
174-
out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;
175-
out->unbounded_req = rq_regs->unbounded_request_enabled;
176-
177-
memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));
178-
out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;
179-
out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;
180-
out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
181-
out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;
182-
out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;
183-
out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;
184-
out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;
185-
out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;
186-
out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;
187-
out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;
188-
out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;
189-
out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;
190-
out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;
191-
out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;
192-
out->dlg_regs.refcyc_per_tdlut_group = disp_dlg_regs->refcyc_per_tdlut_group;
193-
out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;
194-
out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;
195-
//out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;
196-
//out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;
197-
out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;
198-
out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;
199-
//out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;
200-
//out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;
201-
out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;
202-
out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;
203-
out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;
204-
out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;
205-
//out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;
206-
//out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;
207-
//out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;
208-
//out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;
209-
out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;
210-
out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;
211-
out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;
212-
out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;
213-
out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;
214-
out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;
215-
out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;
216-
out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;
217-
out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;
218-
out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;
219-
//out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;
220-
//out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;
221-
out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
222-
out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;
223-
out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;
224-
out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;
225-
226-
memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));
227-
out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;
228-
out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
229-
out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;
230-
out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;
231-
out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;
232-
out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;
233-
out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;
234-
//out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;
235-
out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;
236-
out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;
237-
out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;
238-
//out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;
239-
out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;
240-
out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;
241-
out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;
242-
//out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;
243-
out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;
244-
out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;
245-
out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;
246-
//out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;
150+
union dml2_global_sync_programming *global_sync = &stream_programming->global_sync;
151+
152+
if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
153+
/* phantom has its own global sync */
154+
global_sync = &stream_programming->phantom_stream.global_sync;
155+
}
156+
157+
memcpy(&pipe_ctx->global_sync,
158+
global_sync,
159+
sizeof(union dml2_global_sync_programming));
247160
}
248161

249162
void dml21_populate_mall_allocation_size(struct dc_state *context,
@@ -301,28 +214,16 @@ void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *contex
301214
{
302215
unsigned int pipe_reg_index = 0;
303216

304-
dml21_populate_pipe_ctx_dlg_params(dml_ctx, context, pipe_ctx, stream_prog);
217+
dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);
305218
find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index);
306219

307220
if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
308221
memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));
309222
pipe_ctx->unbounded_req = false;
310-
311-
/* legacy only, should be removed later */
312-
dml21_update_pipe_ctx_dchub_regs(&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->rq_regs,
313-
&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->dlg_regs,
314-
&pln_prog->phantom_plane.pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx);
315-
316223
pipe_ctx->det_buffer_size_kb = 0;
317224
} else {
318225
memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));
319226
pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled;
320-
321-
/* legacy only, should be removed later */
322-
dml21_update_pipe_ctx_dchub_regs(&pln_prog->pipe_regs[pipe_reg_index]->rq_regs,
323-
&pln_prog->pipe_regs[pipe_reg_index]->dlg_regs,
324-
&pln_prog->pipe_regs[pipe_reg_index]->ttu_regs, pipe_ctx);
325-
326227
pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64;
327228
}
328229

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