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Andy Yanvinodkoul
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phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the corresponding set flags are set
According documentation of phy_configure_opts_dp, at the configure stage, link rates should only be verify/configure when set_rate flag is set, the same applies to lanes and voltage. So do it as the documentation says. Because voltage setting depends on the lanes, link rates set previously, so record the link rates and lanes at it's verify stage. Signed-off-by: Andy Yan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/phy/rockchip/phy-rockchip-usbdp.c

Lines changed: 53 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,8 @@ struct rk_udphy {
187187
u32 dp_aux_din_sel;
188188
bool dp_sink_hpd_sel;
189189
bool dp_sink_hpd_cfg;
190+
unsigned int link_rate;
191+
unsigned int lanes;
190192
u8 bw;
191193
int id;
192194

@@ -1103,61 +1105,64 @@ static int rk_udphy_dp_phy_power_off(struct phy *phy)
11031105
return 0;
11041106
}
11051107

1106-
static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
1108+
/*
1109+
* Verify link rate
1110+
*/
1111+
static int rk_udphy_dp_phy_verify_link_rate(struct rk_udphy *udphy,
1112+
struct phy_configure_opts_dp *dp)
11071113
{
1108-
switch (link_rate) {
1114+
switch (dp->link_rate) {
11091115
case 1620:
11101116
case 2700:
11111117
case 5400:
11121118
case 8100:
1119+
udphy->link_rate = dp->link_rate;
11131120
break;
1114-
11151121
default:
11161122
return -EINVAL;
11171123
}
11181124

11191125
return 0;
11201126
}
11211127

1122-
static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy,
1123-
struct phy_configure_opts_dp *dp)
1128+
static int rk_udphy_dp_phy_verify_lanes(struct rk_udphy *udphy,
1129+
struct phy_configure_opts_dp *dp)
11241130
{
1125-
int i, ret;
1126-
1127-
/* If changing link rate was required, verify it's supported. */
1128-
ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate);
1129-
if (ret)
1130-
return ret;
1131-
1132-
/* Verify lane count. */
11331131
switch (dp->lanes) {
11341132
case 1:
11351133
case 2:
11361134
case 4:
11371135
/* valid lane count. */
1136+
udphy->lanes = dp->lanes;
11381137
break;
11391138

11401139
default:
11411140
return -EINVAL;
11421141
}
11431142

1144-
/*
1145-
* If changing voltages is required, check swing and pre-emphasis
1146-
* levels, per-lane.
1147-
*/
1148-
if (dp->set_voltages) {
1149-
/* Lane count verified previously. */
1150-
for (i = 0; i < dp->lanes; i++) {
1151-
if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1152-
return -EINVAL;
1143+
return 0;
1144+
}
11531145

1154-
/*
1155-
* Sum of voltage swing and pre-emphasis levels cannot
1156-
* exceed 3.
1157-
*/
1158-
if (dp->voltage[i] + dp->pre[i] > 3)
1159-
return -EINVAL;
1160-
}
1146+
/*
1147+
* If changing voltages is required, check swing and pre-emphasis
1148+
* levels, per-lane.
1149+
*/
1150+
static int rk_udphy_dp_phy_verify_voltages(struct rk_udphy *udphy,
1151+
struct phy_configure_opts_dp *dp)
1152+
{
1153+
int i;
1154+
1155+
/* Lane count verified previously. */
1156+
for (i = 0; i < udphy->lanes; i++) {
1157+
if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1158+
return -EINVAL;
1159+
1160+
/*
1161+
* Sum of voltage swing and pre-emphasis levels cannot
1162+
* exceed 3.
1163+
*/
1164+
if (dp->voltage[i] + dp->pre[i] > 3)
1165+
return -EINVAL;
11611166
}
11621167

11631168
return 0;
@@ -1197,9 +1202,23 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
11971202
u32 i, val, lane;
11981203
int ret;
11991204

1200-
ret = rk_udphy_dp_phy_verify_config(udphy, dp);
1201-
if (ret)
1202-
return ret;
1205+
if (dp->set_rate) {
1206+
ret = rk_udphy_dp_phy_verify_link_rate(udphy, dp);
1207+
if (ret)
1208+
return ret;
1209+
}
1210+
1211+
if (dp->set_lanes) {
1212+
ret = rk_udphy_dp_phy_verify_lanes(udphy, dp);
1213+
if (ret)
1214+
return ret;
1215+
}
1216+
1217+
if (dp->set_voltages) {
1218+
ret = rk_udphy_dp_phy_verify_voltages(udphy, dp);
1219+
if (ret)
1220+
return ret;
1221+
}
12031222

12041223
if (dp->set_rate) {
12051224
regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
@@ -1244,9 +1263,9 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
12441263
}
12451264

12461265
if (dp->set_voltages) {
1247-
for (i = 0; i < dp->lanes; i++) {
1266+
for (i = 0; i < udphy->lanes; i++) {
12481267
lane = udphy->dp_lane_sel[i];
1249-
switch (dp->link_rate) {
1268+
switch (udphy->link_rate) {
12501269
case 1620:
12511270
case 2700:
12521271
regmap_update_bits(udphy->pma_regmap,

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