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Dimitri FedrauNipaLocal
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net: phy: marvell-88q2xxx: align defines
Align some defines. Signed-off-by: Dimitri Fedrau <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Signed-off-by: NipaLocal <nipa@local>
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drivers/net/phy/marvell-88q2xxx.c

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -12,29 +12,29 @@
1212
#include <linux/phy.h>
1313
#include <linux/hwmon.h>
1414

15-
#define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
16-
#define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
17-
#define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
18-
19-
#define MDIO_MMD_AN_MV_STAT 32769
20-
#define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
21-
#define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
22-
#define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
23-
#define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
24-
#define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
25-
26-
#define MDIO_MMD_AN_MV_STAT2 32794
27-
#define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
28-
#define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
29-
#define MDIO_MMD_AN_MV_STAT2_1000BT1 0x4000
30-
31-
#define MDIO_MMD_PCS_MV_RESET_CTRL 32768
32-
#define MDIO_MMD_PCS_MV_RESET_CTRL_TX_DISABLE 0x8
33-
34-
#define MDIO_MMD_PCS_MV_INT_EN 32784
35-
#define MDIO_MMD_PCS_MV_INT_EN_LINK_UP 0x0040
36-
#define MDIO_MMD_PCS_MV_INT_EN_LINK_DOWN 0x0080
37-
#define MDIO_MMD_PCS_MV_INT_EN_100BT1 0x1000
15+
#define PHY_ID_88Q2220_REVB0 (MARVELL_PHY_ID_88Q2220 | 0x1)
16+
#define PHY_ID_88Q2220_REVB1 (MARVELL_PHY_ID_88Q2220 | 0x2)
17+
#define PHY_ID_88Q2220_REVB2 (MARVELL_PHY_ID_88Q2220 | 0x3)
18+
19+
#define MDIO_MMD_AN_MV_STAT 32769
20+
#define MDIO_MMD_AN_MV_STAT_ANEG 0x0100
21+
#define MDIO_MMD_AN_MV_STAT_LOCAL_RX 0x1000
22+
#define MDIO_MMD_AN_MV_STAT_REMOTE_RX 0x2000
23+
#define MDIO_MMD_AN_MV_STAT_LOCAL_MASTER 0x4000
24+
#define MDIO_MMD_AN_MV_STAT_MS_CONF_FAULT 0x8000
25+
26+
#define MDIO_MMD_AN_MV_STAT2 32794
27+
#define MDIO_MMD_AN_MV_STAT2_AN_RESOLVED 0x0800
28+
#define MDIO_MMD_AN_MV_STAT2_100BT1 0x2000
29+
#define MDIO_MMD_AN_MV_STAT2_1000BT1 0x4000
30+
31+
#define MDIO_MMD_PCS_MV_RESET_CTRL 32768
32+
#define MDIO_MMD_PCS_MV_RESET_CTRL_TX_DISABLE 0x8
33+
34+
#define MDIO_MMD_PCS_MV_INT_EN 32784
35+
#define MDIO_MMD_PCS_MV_INT_EN_LINK_UP 0x0040
36+
#define MDIO_MMD_PCS_MV_INT_EN_LINK_DOWN 0x0080
37+
#define MDIO_MMD_PCS_MV_INT_EN_100BT1 0x1000
3838

3939
#define MDIO_MMD_PCS_MV_GPIO_INT_STAT 32785
4040
#define MDIO_MMD_PCS_MV_GPIO_INT_STAT_LINK_UP 0x0040
@@ -80,19 +80,19 @@
8080
#define MDIO_MMD_PCS_MV_100BT1_STAT1_REMOTE_RX 0x2000
8181
#define MDIO_MMD_PCS_MV_100BT1_STAT1_LOCAL_MASTER 0x4000
8282

83-
#define MDIO_MMD_PCS_MV_100BT1_STAT2 33033
84-
#define MDIO_MMD_PCS_MV_100BT1_STAT2_JABBER 0x0001
85-
#define MDIO_MMD_PCS_MV_100BT1_STAT2_POL 0x0002
86-
#define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK 0x0004
87-
#define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE 0x0008
83+
#define MDIO_MMD_PCS_MV_100BT1_STAT2 33033
84+
#define MDIO_MMD_PCS_MV_100BT1_STAT2_JABBER 0x0001
85+
#define MDIO_MMD_PCS_MV_100BT1_STAT2_POL 0x0002
86+
#define MDIO_MMD_PCS_MV_100BT1_STAT2_LINK 0x0004
87+
#define MDIO_MMD_PCS_MV_100BT1_STAT2_ANGE 0x0008
8888

8989
#define MDIO_MMD_PCS_MV_100BT1_INT_EN 33042
9090
#define MDIO_MMD_PCS_MV_100BT1_INT_EN_LINKEVENT 0x0400
9191

9292
#define MDIO_MMD_PCS_MV_COPPER_INT_STAT 33043
9393
#define MDIO_MMD_PCS_MV_COPPER_INT_STAT_LINKEVENT 0x0400
9494

95-
#define MDIO_MMD_PCS_MV_RX_STAT 33328
95+
#define MDIO_MMD_PCS_MV_RX_STAT 33328
9696

9797
#define MDIO_MMD_PCS_MV_TDR_RESET 65226
9898
#define MDIO_MMD_PCS_MV_TDR_RESET_TDR_RST 0x1000
@@ -115,8 +115,8 @@
115115

116116
#define MDIO_MMD_PCS_MV_TDR_OFF_CUTOFF 65246
117117

118-
#define MV88Q2XXX_LED_INDEX_TX_ENABLE 0
119-
#define MV88Q2XXX_LED_INDEX_GPIO 1
118+
#define MV88Q2XXX_LED_INDEX_TX_ENABLE 0
119+
#define MV88Q2XXX_LED_INDEX_GPIO 1
120120

121121
struct mv88q2xxx_priv {
122122
bool enable_temp;

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