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61 | 61 |
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62 | 62 | // Status register for MOTU 896 (0x'ffff'f000'0b14).
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63 | 63 | //
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64 |
| -// 0x20000000: fetch PCM frames from communication IC to DAC. |
| 64 | +// 0xf0000000: enable physical and stream input to DAC. |
| 65 | +// 0x80000000: disable |
| 66 | +// 0x40000000: disable |
| 67 | +// 0x20000000: enable (prior to the other bits) |
| 68 | +// 0x10000000: disable |
| 69 | +// 0x00000000: disable |
65 | 70 | // 0x08000000: speed of word clock signal output on BNC interface.
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66 |
| -// 0x00000000: follow to system clock. |
67 |
| -// 0x08000000: half of system clock. |
68 |
| -// 0x01000000: Route main output to headphone output. |
69 |
| -// 0x00ffff00: input to monitor. |
70 |
| -// 0x00000000: none |
| 71 | +// 0x00000000: force to low rate (44.1/48.0 kHz). |
| 72 | +// 0x08000000: follow to system clock. |
| 73 | +// 0x04000000: something relevant to clock. |
| 74 | +// 0x03000000: enable output. |
| 75 | +// 0x02000000: enabled irreversibly once standing unless the device voluntarily disables it. |
| 76 | +// 0x01000000: enabled irreversibly once standing unless the device voluntarily disables it. |
| 77 | +// 0x00ffff00: monitor input mode. |
| 78 | +// 0x00000000: disabled |
71 | 79 | // 0x00004800: analog-1/2
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72 | 80 | // 0x00005a00: analog-3/4
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73 | 81 | // 0x00006c00: analog-5/6
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83 | 91 | // 0x00007f00: analog-8
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84 | 92 | // 0x00104000: AES/EBU-1
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85 | 93 | // 0x00104900: AES/EBU-2
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86 |
| -// 0x00000060: sample rate conversin for AES/EBU input/output. |
| 94 | +// 0x00000060: sample rate conversion for AES/EBU input/output. |
87 | 95 | // 0x00000000: None
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88 | 96 | // 0x00000020: input signal is converted to system rate
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89 | 97 | // 0x00000040: output is slave to input, ignoring system rate
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97 | 105 | // 0x00000000: internal
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98 | 106 | // 0x00000001: ADAT on optical interface
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99 | 107 | // 0x00000002: AES/EBU on XLR
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| 108 | +// 0x00000003: source packet header (SPH) |
100 | 109 | // 0x00000004: word clock on BNC
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101 | 110 | // 0x00000005: ADAT on Dsub 9pin
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102 | 111 |
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103 | 112 | #define CLK_896_STATUS_OFFSET 0x0b14
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104 | 113 | #define CLK_896_STATUS_FLAG_FETCH_ENABLE 0x20000000
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105 |
| -#define CLK_896_STATUS_FLAG_MAIN_TO_HP 0x01000000 |
| 114 | +#define CLK_896_STATUS_FLAG_OUTPUT_ON 0x03000000 |
106 | 115 | #define CLK_896_STATUS_MASK_SRC 0x00000007
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107 | 116 | #define CLK_896_STATUS_FLAG_SRC_INTERNAL 0x00000000
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108 | 117 | #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000001
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109 | 118 | #define CLK_896_STATUS_FLAG_SRC_AESEBU 0x00000002
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| 119 | +#define CLK_896_STATUS_FLAG_SRC_SPH 0x00000003 |
110 | 120 | #define CLK_896_STATUS_FLAG_SRC_WORD 0x00000004
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111 | 121 | #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000005
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112 | 122 | #define CLK_896_STATUS_MASK_RATE 0x00000018
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@@ -304,6 +314,9 @@ static int get_clock_source_896(struct snd_motu *motu, enum snd_motu_clock_sourc
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304 | 314 | case CLK_896_STATUS_FLAG_SRC_AESEBU:
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305 | 315 | *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
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306 | 316 | break;
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| 317 | + case CLK_896_STATUS_FLAG_SRC_SPH: |
| 318 | + *src = SND_MOTU_CLOCK_SOURCE_SPH; |
| 319 | + break; |
307 | 320 | case CLK_896_STATUS_FLAG_SRC_WORD:
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308 | 321 | *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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309 | 322 | break;
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@@ -362,9 +375,9 @@ static int switch_fetching_mode_896(struct snd_motu *motu, bool enable)
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362 | 375 | return err;
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363 | 376 | data = be32_to_cpu(reg);
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364 | 377 |
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365 |
| - data &= ~(CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_MAIN_TO_HP); |
| 378 | + data &= ~CLK_896_STATUS_FLAG_FETCH_ENABLE; |
366 | 379 | if (enable)
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367 |
| - data |= (CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_MAIN_TO_HP); |
| 380 | + data |= CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_OUTPUT_ON; |
368 | 381 |
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369 | 382 | reg = cpu_to_be32(data);
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370 | 383 | return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
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