igc: Add netdev

Now that we have the ability to configure the basic settings on the device
we can start allocating and configuring a netdev for the interface.

Signed-off-by: Sasha Neftin <[email protected]>
Tested-by: Aaron Brown <[email protected]>
Signed-off-by: Jeff Kirsher <[email protected]>

Author: aneftin

drivers/net/ethernet/intel/igc/igc.h

@@ -28,15 +28,63 @@
 extern char igc_driver_name[];
 extern char igc_driver_version[];
 
+/* Transmit and receive queues */
+#define IGC_MAX_RX_QUEUES		4
+#define IGC_MAX_TX_QUEUES		4
+
+#define MAX_Q_VECTORS			8
+#define MAX_STD_JUMBO_FRAME_SIZE	9216
+
+enum igc_state_t {
+	__IGC_TESTING,
+	__IGC_RESETTING,
+	__IGC_DOWN,
+	__IGC_PTP_TX_IN_PROGRESS,
+};
+
+struct igc_q_vector {
+	struct igc_adapter *adapter;    /* backlink */
+
+	struct napi_struct napi;
+};
+
+struct igc_mac_addr {
+	u8 addr[ETH_ALEN];
+	u8 queue;
+	u8 state; /* bitmask */
+};
+
+#define IGC_MAC_STATE_DEFAULT	0x1
+#define IGC_MAC_STATE_MODIFIED	0x2
+#define IGC_MAC_STATE_IN_USE	0x4
+
 /* Board specific private data structure */
 struct igc_adapter {
+	struct net_device *netdev;
+
+	unsigned long state;
+	unsigned int flags;
+	unsigned int num_q_vectors;
+	u16 link_speed;
+	u16 link_duplex;
+
+	u8 port_num;
+
 	u8 __iomem *io_addr;
+	struct work_struct watchdog_task;
+
+	int msg_enable;
+	u32 max_frame_size;
 
 	/* OS defined structs */
 	struct pci_dev *pdev;
 
 	/* structs defined in igc_hw.h */
 	struct igc_hw hw;
+
+	struct igc_q_vector *q_vector[MAX_Q_VECTORS];
+
+	struct igc_mac_addr *mac_table;
 };
 
 #endif /* _IGC_H_ */

drivers/net/ethernet/intel/igc/igc_defines.h

@@ -4,10 +4,22 @@
 #ifndef _IGC_DEFINES_H_
 #define _IGC_DEFINES_H_
 
+#define IGC_CTRL_EXT_DRV_LOAD	0x10000000 /* Drv loaded bit for FW */
+
 /* PCI Bus Info */
 #define PCIE_DEVICE_CONTROL2		0x28
 #define PCIE_DEVICE_CONTROL2_16ms	0x0005
 
+/* Receive Address
+ * Number of high/low register pairs in the RAR. The RAR (Receive Address
+ * Registers) holds the directed and multicast addresses that we monitor.
+ * Technically, we have 16 spots.  However, we reserve one of these spots
+ * (RAR[15]) for our directed address used by controllers with
+ * manageability enabled, allowing us room for 15 multicast addresses.
+ */
+#define IGC_RAH_AV		0x80000000 /* Receive descriptor valid */
+#define IGC_RAH_POOL_1		0x00040000
+
 /* Error Codes */
 #define IGC_SUCCESS			0
 #define IGC_ERR_NVM			1
@@ -17,6 +29,9 @@
 #define IGC_ERR_MAC_INIT		5
 #define IGC_ERR_RESET			9
 
+/* PBA constants */
+#define IGC_PBA_34K		0x0022
+
 /* Device Status */
 #define IGC_STATUS_FD		0x00000001      /* Full duplex.0=half,1=full */
 #define IGC_STATUS_LU		0x00000002      /* Link up.0=no,1=link */

drivers/net/ethernet/intel/igc/igc_hw.h

@@ -59,6 +59,7 @@ struct igc_mac_info {
 
 	bool autoneg;
 	bool autoneg_failed;
+	bool get_link_status;
 };
 
 struct igc_bus_info {