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torvaldstorvalds
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Merge tag 'drm-fixes-2025-05-10' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Weekly drm fixes, bit bigger than last week, but overall amdgpu/xe with some ivpu bits and a random few fixes, and dropping the ttm_backup struct which wrapped struct file and was recently frowned at. drm: - Fix overflow when generating wedged event ttm: - Fix documentation - Remove struct ttm_backup panel: - simple: Fix timings for AUO G101EVN010 amdgpu: - DC FP fixes - Freesync fix - DMUB AUX fixes - VCN fix - Hibernation fixes - HDP fixes xe: - Prevent PF queue overflow - Hold all forcewake during mocs test - Remove GSC flush on reset path - Fix forcewake put on error path - Fix runtime warning when building without svm i915: - Fix oops on resume after disconnecting DP MST sinks during suspend - Fix SPLC num_waiters refcounting ivpu: - Increase timeouts - Fix deadlock in cmdq ioctl - Unlock mutices in correct order v3d: - Avoid memory leak in job handling" * tag 'drm-fixes-2025-05-10' of https://gitlab.freedesktop.org/drm/kernel: (32 commits) drm/i915/dp: Fix determining SST/MST mode during MTP TU state computation drm/xe: Add config control for svm flush work drm/xe: Release force wake first then runtime power drm/xe/gsc: do not flush the GSC worker from the reset path drm/xe/tests/mocs: Hold XE_FORCEWAKE_ALL for LNCF regs drm/xe: Add page queue multiplier drm/amdgpu/hdp7: use memcfg register to post the write for HDP flush drm/amdgpu/hdp6: use memcfg register to post the write for HDP flush drm/amdgpu/hdp5.2: use memcfg register to post the write for HDP flush drm/amdgpu/hdp5: use memcfg register to post the write for HDP flush drm/amdgpu/hdp4: use memcfg register to post the write for HDP flush drm/amdgpu: fix pm notifier handling Revert "drm/amd: Stop evicting resources on APUs in suspend" drm/amdgpu/vcn: using separate VCN1_AON_SOC offset drm/amd/display: Fix wrong handling for AUX_DEFER case drm/amd/display: Copy AUX read reply data whenever length > 0 drm/amd/display: Remove incorrect checking in dmub aux handler drm/amd/display: Fix the checking condition in dmub aux handling drm/amd/display: Shift DMUB AUX reply command if necessary drm/amd/display: Call FP Protect Before Mode Programming/Mode Support ...
2 parents 50358c2 + c2c64ed commit ea34704

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47 files changed

+285
-195
lines changed

‎drivers/accel/ivpu/ivpu_hw.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ static void timeouts_init(struct ivpu_device *vdev)
119119
else
120120
vdev->timeout.autosuspend = 100;
121121
vdev->timeout.d0i3_entry_msg = 5;
122-
vdev->timeout.state_dump_msg = 10;
122+
vdev->timeout.state_dump_msg = 100;
123123
}
124124
}
125125

‎drivers/accel/ivpu/ivpu_job.c

Lines changed: 25 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -681,8 +681,8 @@ static int ivpu_job_submit(struct ivpu_job *job, u8 priority, u32 cmdq_id)
681681
err_erase_xa:
682682
xa_erase(&vdev->submitted_jobs_xa, job->job_id);
683683
err_unlock:
684-
mutex_unlock(&vdev->submitted_jobs_lock);
685684
mutex_unlock(&file_priv->lock);
685+
mutex_unlock(&vdev->submitted_jobs_lock);
686686
ivpu_rpm_put(vdev);
687687
return ret;
688688
}
@@ -874,15 +874,21 @@ int ivpu_cmdq_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *
874874
int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
875875
{
876876
struct ivpu_file_priv *file_priv = file->driver_priv;
877+
struct ivpu_device *vdev = file_priv->vdev;
877878
struct drm_ivpu_cmdq_create *args = data;
878879
struct ivpu_cmdq *cmdq;
880+
int ret;
879881

880-
if (!ivpu_is_capable(file_priv->vdev, DRM_IVPU_CAP_MANAGE_CMDQ))
882+
if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ))
881883
return -ENODEV;
882884

883885
if (args->priority > DRM_IVPU_JOB_PRIORITY_REALTIME)
884886
return -EINVAL;
885887

888+
ret = ivpu_rpm_get(vdev);
889+
if (ret < 0)
890+
return ret;
891+
886892
mutex_lock(&file_priv->lock);
887893

888894
cmdq = ivpu_cmdq_create(file_priv, ivpu_job_to_jsm_priority(args->priority), false);
@@ -891,6 +897,8 @@ int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file *
891897

892898
mutex_unlock(&file_priv->lock);
893899

900+
ivpu_rpm_put(vdev);
901+
894902
return cmdq ? 0 : -ENOMEM;
895903
}
896904

@@ -900,28 +908,35 @@ int ivpu_cmdq_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file
900908
struct ivpu_device *vdev = file_priv->vdev;
901909
struct drm_ivpu_cmdq_destroy *args = data;
902910
struct ivpu_cmdq *cmdq;
903-
u32 cmdq_id;
911+
u32 cmdq_id = 0;
904912
int ret;
905913

906914
if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_MANAGE_CMDQ))
907915
return -ENODEV;
908916

917+
ret = ivpu_rpm_get(vdev);
918+
if (ret < 0)
919+
return ret;
920+
909921
mutex_lock(&file_priv->lock);
910922

911923
cmdq = xa_load(&file_priv->cmdq_xa, args->cmdq_id);
912924
if (!cmdq || cmdq->is_legacy) {
913925
ret = -ENOENT;
914-
goto err_unlock;
926+
} else {
927+
cmdq_id = cmdq->id;
928+
ivpu_cmdq_destroy(file_priv, cmdq);
929+
ret = 0;
915930
}
916931

917-
cmdq_id = cmdq->id;
918-
ivpu_cmdq_destroy(file_priv, cmdq);
919932
mutex_unlock(&file_priv->lock);
920-
ivpu_cmdq_abort_all_jobs(vdev, file_priv->ctx.id, cmdq_id);
921-
return 0;
922933

923-
err_unlock:
924-
mutex_unlock(&file_priv->lock);
934+
/* Abort any pending jobs only if cmdq was destroyed */
935+
if (!ret)
936+
ivpu_cmdq_abort_all_jobs(vdev, file_priv->ctx.id, cmdq_id);
937+
938+
ivpu_rpm_put(vdev);
939+
925940
return ret;
926941
}
927942

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,11 +1614,9 @@ static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_cap
16141614
#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
16151615
bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
16161616
bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1617-
void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
16181617
#else
16191618
static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
16201619
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1621-
static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
16221620
#endif
16231621

16241622
void amdgpu_register_gpu_instance(struct amdgpu_device *adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1533,22 +1533,4 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
15331533
#endif /* CONFIG_AMD_PMC */
15341534
}
15351535

1536-
/**
1537-
* amdgpu_choose_low_power_state
1538-
*
1539-
* @adev: amdgpu_device_pointer
1540-
*
1541-
* Choose the target low power state for the GPU
1542-
*/
1543-
void amdgpu_choose_low_power_state(struct amdgpu_device *adev)
1544-
{
1545-
if (adev->in_runpm)
1546-
return;
1547-
1548-
if (amdgpu_acpi_is_s0ix_active(adev))
1549-
adev->in_s0ix = true;
1550-
else if (amdgpu_acpi_is_s3_active(adev))
1551-
adev->in_s3 = true;
1552-
}
1553-
15541536
#endif /* CONFIG_SUSPEND */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 7 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -4907,28 +4907,20 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
49074907
* @data: data
49084908
*
49094909
* This function is called when the system is about to suspend or hibernate.
4910-
* It is used to evict resources from the device before the system goes to
4911-
* sleep while there is still access to swap.
4910+
* It is used to set the appropriate flags so that eviction can be optimized
4911+
* in the pm prepare callback.
49124912
*/
49134913
static int amdgpu_device_pm_notifier(struct notifier_block *nb, unsigned long mode,
49144914
void *data)
49154915
{
49164916
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, pm_nb);
4917-
int r;
49184917

49194918
switch (mode) {
49204919
case PM_HIBERNATION_PREPARE:
49214920
adev->in_s4 = true;
4922-
fallthrough;
4923-
case PM_SUSPEND_PREPARE:
4924-
r = amdgpu_device_evict_resources(adev);
4925-
/*
4926-
* This is considered non-fatal at this time because
4927-
* amdgpu_device_prepare() will also fatally evict resources.
4928-
* See https://gitlab.freedesktop.org/drm/amd/-/issues/3781
4929-
*/
4930-
if (r)
4931-
drm_warn(adev_to_drm(adev), "Failed to evict resources, freeze active processes if problems occur: %d\n", r);
4921+
break;
4922+
case PM_POST_HIBERNATION:
4923+
adev->in_s4 = false;
49324924
break;
49334925
}
49344926

@@ -4949,15 +4941,13 @@ int amdgpu_device_prepare(struct drm_device *dev)
49494941
struct amdgpu_device *adev = drm_to_adev(dev);
49504942
int i, r;
49514943

4952-
amdgpu_choose_low_power_state(adev);
4953-
49544944
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
49554945
return 0;
49564946

49574947
/* Evict the majority of BOs before starting suspend sequence */
49584948
r = amdgpu_device_evict_resources(adev);
49594949
if (r)
4960-
goto unprepare;
4950+
return r;
49614951

49624952
flush_delayed_work(&adev->gfx.gfx_off_delay_work);
49634953

@@ -4968,15 +4958,10 @@ int amdgpu_device_prepare(struct drm_device *dev)
49684958
continue;
49694959
r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]);
49704960
if (r)
4971-
goto unprepare;
4961+
return r;
49724962
}
49734963

49744964
return 0;
4975-
4976-
unprepare:
4977-
adev->in_s0ix = adev->in_s3 = adev->in_s4 = false;
4978-
4979-
return r;
49804965
}
49814966

49824967
/**

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2615,13 +2615,8 @@ static int amdgpu_pmops_freeze(struct device *dev)
26152615
static int amdgpu_pmops_thaw(struct device *dev)
26162616
{
26172617
struct drm_device *drm_dev = dev_get_drvdata(dev);
2618-
struct amdgpu_device *adev = drm_to_adev(drm_dev);
2619-
int r;
2620-
2621-
r = amdgpu_device_resume(drm_dev, true);
2622-
adev->in_s4 = false;
26232618

2624-
return r;
2619+
return amdgpu_device_resume(drm_dev, true);
26252620
}
26262621

26272622
static int amdgpu_pmops_poweroff(struct device *dev)
@@ -2634,9 +2629,6 @@ static int amdgpu_pmops_poweroff(struct device *dev)
26342629
static int amdgpu_pmops_restore(struct device *dev)
26352630
{
26362631
struct drm_device *drm_dev = dev_get_drvdata(dev);
2637-
struct amdgpu_device *adev = drm_to_adev(drm_dev);
2638-
2639-
adev->in_s4 = false;
26402632

26412633
return amdgpu_device_resume(drm_dev, true);
26422634
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,6 @@
6666
#define VCN_ENC_CMD_REG_WAIT 0x0000000c
6767

6868
#define VCN_AON_SOC_ADDRESS_2_0 0x1f800
69-
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
7069
#define VCN_VID_IP_ADDRESS_2_0 0x0
7170
#define VCN_AON_IP_ADDRESS_2_0 0x30000
7271

‎drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,12 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
4141
{
4242
if (!ring || !ring->funcs->emit_wreg) {
4343
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
44-
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
44+
/* We just need to read back a register to post the write.
45+
* Reading back the remapped register causes problems on
46+
* some platforms so just read back the memory size register.
47+
*/
48+
if (adev->nbio.funcs->get_memsize)
49+
adev->nbio.funcs->get_memsize(adev);
4550
} else {
4651
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
4752
}

‎drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,12 @@ static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
3232
{
3333
if (!ring || !ring->funcs->emit_wreg) {
3434
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
35-
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
35+
/* We just need to read back a register to post the write.
36+
* Reading back the remapped register causes problems on
37+
* some platforms so just read back the memory size register.
38+
*/
39+
if (adev->nbio.funcs->get_memsize)
40+
adev->nbio.funcs->get_memsize(adev);
3641
} else {
3742
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
3843
}

‎drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,17 @@ static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
3333
if (!ring || !ring->funcs->emit_wreg) {
3434
WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
3535
0);
36-
RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
36+
if (amdgpu_sriov_vf(adev)) {
37+
/* this is fine because SR_IOV doesn't remap the register */
38+
RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
39+
} else {
40+
/* We just need to read back a register to post the write.
41+
* Reading back the remapped register causes problems on
42+
* some platforms so just read back the memory size register.
43+
*/
44+
if (adev->nbio.funcs->get_memsize)
45+
adev->nbio.funcs->get_memsize(adev);
46+
}
3747
} else {
3848
amdgpu_ring_emit_wreg(ring,
3949
(adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,

‎drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,12 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
3535
{
3636
if (!ring || !ring->funcs->emit_wreg) {
3737
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
38-
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
38+
/* We just need to read back a register to post the write.
39+
* Reading back the remapped register causes problems on
40+
* some platforms so just read back the memory size register.
41+
*/
42+
if (adev->nbio.funcs->get_memsize)
43+
adev->nbio.funcs->get_memsize(adev);
3944
} else {
4045
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
4146
}

‎drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,12 @@ static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
3232
{
3333
if (!ring || !ring->funcs->emit_wreg) {
3434
WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
35-
RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
35+
/* We just need to read back a register to post the write.
36+
* Reading back the remapped register causes problems on
37+
* some platforms so just read back the memory size register.
38+
*/
39+
if (adev->nbio.funcs->get_memsize)
40+
adev->nbio.funcs->get_memsize(adev);
3641
} else {
3742
amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
3843
}

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939

4040
#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
4141
#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42+
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
4243

4344
#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
4445
#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939

4040
#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
4141
#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
42+
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
4243

4344
#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
4445
#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f

‎drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
4040

4141
#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
4242
#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
43+
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
4344

4445
#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
4546
#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f

‎drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@
4646

4747
#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
4848
#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
49+
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
4950

5051
#define VCN_HARVEST_MMSCH 0
5152

@@ -614,7 +615,8 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
614615

615616
/* VCN global tiling registers */
616617
WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
617-
VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
618+
VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
619+
adev->gfx.config.gb_addr_config, 0, indirect);
618620
}
619621

620622
/**

‎drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@
4545

4646
#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
4747
#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
48+
#define VCN1_AON_SOC_ADDRESS_3_0 0x48000
4849

4950
static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
5051
SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),

‎drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@
4646

4747
#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
4848
#define VCN1_VID_SOC_ADDRESS_3_0 (0x48300 + 0x38000)
49+
#define VCN1_AON_SOC_ADDRESS_3_0 (0x48000 + 0x38000)
4950

5051
#define VCN_HARVEST_MMSCH 0
5152

‎drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -533,7 +533,8 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
533533

534534
/* VCN global tiling registers */
535535
WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
536-
VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
536+
VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
537+
adev->gfx.config.gb_addr_config, 0, indirect);
537538

538539
return;
539540
}

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