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drm/amd/display: To apply the adjusted DP ref clock for DP devices
[Why]
For some pixel clock margin sensitive external monitor,
we could not keep original DP ref clock for the ASICs
supported SSC DP ref clock.
[How]
From slicon design team's comment,
we have to apply the adjusted DP ref clock for
DP devices.
DP 128b (DP2) signals uses the DTBCLK not DP ref.
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Yiling Chen <[email protected]>
Signed-off-by: Zaeem Mohamed <[email protected]>
Tested-by: Mark Broadworth <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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