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Yiling Chenalexdeucher
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drm/amd/display: To apply the adjusted DP ref clock for DP devices
[Why] For some pixel clock margin sensitive external monitor, we could not keep original DP ref clock for the ASICs supported SSC DP ref clock. [How] From slicon design team's comment, we have to apply the adjusted DP ref clock for DP devices. DP 128b (DP2) signals uses the DTBCLK not DP ref. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Yiling Chen <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Mark Broadworth <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -976,11 +976,12 @@ static bool dcn31_program_pix_clk(
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struct bp_pixel_clock_parameters bp_pc_params = {0};
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enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
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979-
// Apply ssed(spread spectrum) dpref clock for edp only.
980-
if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0
981-
&& pix_clk_params->signal_type == SIGNAL_TYPE_EDP
982-
&& encoding == DP_8b_10b_ENCODING)
979+
// Apply ssed(spread spectrum) dpref clock for edp and dp
980+
if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&
981+
dc_is_dp_signal(pix_clk_params->signal_type) &&
982+
encoding == DP_8b_10b_ENCODING)
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dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;
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// For these signal types Driver to program DP_DTO without calling VBIOS Command table
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if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
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if (e) {

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