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phy: qcom-qmp-combo,usb: add support for separate PCS_USB region
Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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-108
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3 files changed

+163
-108
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‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c

Lines changed: 36 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -155,8 +155,10 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
155155
[QPHY_START_CTRL] = 0x44,
156156
[QPHY_PCS_STATUS] = 0x14,
157157
[QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
158-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
159-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
158+
159+
/* In PCS_USB */
160+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
161+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
160162
};
161163

162164
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -451,6 +453,9 @@ static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
451453
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
452454
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
453455
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
456+
};
457+
458+
static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
454459
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
455460
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
456461
};
@@ -520,6 +525,9 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
520525
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
521526
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
522527
QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
528+
};
529+
530+
static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
523531
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
524532
QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
525533
};
@@ -634,6 +642,8 @@ struct qmp_phy_cfg {
634642
int rx_tbl_num;
635643
const struct qmp_phy_init_tbl *pcs_tbl;
636644
int pcs_tbl_num;
645+
const struct qmp_phy_init_tbl *pcs_usb_tbl;
646+
int pcs_usb_tbl_num;
637647

638648
/* Init sequence for DP PHY block link rates */
639649
const struct qmp_phy_init_tbl *serdes_tbl_rbr;
@@ -679,6 +689,10 @@ struct qmp_phy_cfg {
679689
bool has_phy_dp_com_ctrl;
680690
/* true, if PHY has secondary tx/rx lanes to be configured */
681691
bool is_dual_lane_phy;
692+
693+
/* Offset from PCS to PCS_USB region */
694+
unsigned int pcs_usb_offset;
695+
682696
};
683697

684698
struct qmp_phy_combo_cfg {
@@ -698,6 +712,7 @@ struct qmp_phy_combo_cfg {
698712
* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
699713
* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
700714
* @pcs_misc: iomapped memory space for lane's pcs_misc
715+
* @pcs_usb: iomapped memory space for lane's pcs_usb
701716
* @pipe_clk: pipe clock
702717
* @index: lane index
703718
* @qmp: QMP phy to which this lane belongs
@@ -717,6 +732,7 @@ struct qmp_phy {
717732
void __iomem *tx2;
718733
void __iomem *rx2;
719734
void __iomem *pcs_misc;
735+
void __iomem *pcs_usb;
720736
struct clk *pipe_clk;
721737
unsigned int index;
722738
struct qcom_qmp *qmp;
@@ -905,13 +921,16 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
905921
.rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
906922
.pcs_tbl = sm8150_usb3_pcs_tbl,
907923
.pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
924+
.pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
925+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
908926
.clk_list = qmp_v4_phy_clk_l,
909927
.num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
910928
.reset_list = msm8996_usb3phy_reset_l,
911929
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
912930
.vreg_list = qmp_phy_vreg_l,
913931
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
914932
.regs = qmp_v4_usb3phy_regs_layout,
933+
.pcs_usb_offset = 0x300,
915934

916935
.start_ctrl = SERDES_START | PCS_START,
917936
.pwrdn_ctrl = SW_PWRDN,
@@ -978,13 +997,16 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
978997
.rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
979998
.pcs_tbl = sm8250_usb3_pcs_tbl,
980999
.pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1000+
.pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1001+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
9811002
.clk_list = qmp_v4_sm8250_usbphy_clk_l,
9821003
.num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
9831004
.reset_list = msm8996_usb3phy_reset_l,
9841005
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
9851006
.vreg_list = qmp_phy_vreg_l,
9861007
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
9871008
.regs = qmp_v4_usb3phy_regs_layout,
1009+
.pcs_usb_offset = 0x300,
9881010

9891011
.start_ctrl = SERDES_START | PCS_START,
9901012
.pwrdn_ctrl = SW_PWRDN,
@@ -1869,7 +1891,7 @@ static int qcom_qmp_phy_combo_set_mode(struct phy *phy,
18691891
static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
18701892
{
18711893
const struct qmp_phy_cfg *cfg = qphy->cfg;
1872-
void __iomem *pcs = qphy->pcs;
1894+
void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
18731895
void __iomem *pcs_misc = qphy->pcs_misc;
18741896
u32 intr_mask;
18751897

@@ -1880,15 +1902,15 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
18801902
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
18811903

18821904
/* Clear any pending interrupts status */
1883-
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1905+
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
18841906
/* Writing 1 followed by 0 clears the interrupt */
1885-
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1907+
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
18861908

1887-
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1909+
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
18881910
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
18891911

18901912
/* Enable required PHY autonomous mode interrupts */
1891-
qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1913+
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
18921914

18931915
/* Enable i/o clamp_n for autonomous mode */
18941916
if (pcs_misc)
@@ -1898,19 +1920,19 @@ static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy)
18981920
static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy)
18991921
{
19001922
const struct qmp_phy_cfg *cfg = qphy->cfg;
1901-
void __iomem *pcs = qphy->pcs;
1923+
void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs_usb;
19021924
void __iomem *pcs_misc = qphy->pcs_misc;
19031925

19041926
/* Disable i/o clamp_n on resume for normal mode */
19051927
if (pcs_misc)
19061928
qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
19071929

1908-
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1930+
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
19091931
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
19101932

1911-
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1933+
qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
19121934
/* Writing 1 followed by 0 clears the interrupt */
1913-
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1935+
qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
19141936
}
19151937

19161938
static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev)
@@ -2346,6 +2368,9 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
23462368
if (!qphy->pcs)
23472369
return -ENOMEM;
23482370

2371+
if (cfg->pcs_usb_offset)
2372+
qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
2373+
23492374
/*
23502375
* If this is a dual-lane PHY, then there should be registers for the
23512376
* second lane. Some old device trees did not specify this, so fall

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