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clocksource/drivers/timer-ti-dm: Move private defines to the driver
These defines are only used by timer-ti-dm driver. Signed-off-by: Tony Lindgren <[email protected]> Reviewed-by: Janusz Krzysztofik <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Daniel Lezcano <[email protected]>
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‎drivers/clocksource/timer-ti-dm.c

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@@ -33,6 +33,68 @@
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#include <clocksource/timer-ti-dm.h>
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/*
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* timer errata flags
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*
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* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
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* errata prevents us from using posted mode on these devices, unless the
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* timer counter register is never read. For more details please refer to
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* the OMAP3/4/5 errata documents.
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*/
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#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
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/* posted mode types */
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#define OMAP_TIMER_NONPOSTED 0x00
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#define OMAP_TIMER_POSTED 0x01
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/* register offsets with the write pending bit encoded */
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#define WPSHIFT 16
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#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
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| (WP_TCLR << WPSHIFT))
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#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
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| (WP_TCRR << WPSHIFT))
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
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| (WP_TTGR << WPSHIFT))
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#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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| (WP_TMAR << WPSHIFT))
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#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
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| (WP_TPIR << WPSHIFT))
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#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
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| (WP_TNIR << WPSHIFT))
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#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
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| (WP_TCVR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
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(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
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(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
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static u32 omap_reserved_systimers;
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static LIST_HEAD(omap_timer_list);
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static DEFINE_SPINLOCK(dm_timer_lock);

‎include/clocksource/timer-ti-dm.h

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@@ -52,27 +52,13 @@
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#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
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#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
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/* posted mode types */
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#define OMAP_TIMER_NONPOSTED 0x00
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#define OMAP_TIMER_POSTED 0x01
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/* timer capabilities used in hwmod database */
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#define OMAP_TIMER_SECURE 0x80000000
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#define OMAP_TIMER_ALWON 0x40000000
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#define OMAP_TIMER_HAS_PWM 0x20000000
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#define OMAP_TIMER_NEEDS_RESET 0x10000000
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#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
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/*
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* timer errata flags
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*
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* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
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* errata prevents us from using posted mode on these devices, unless the
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* timer counter register is never read. For more details please refer to
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* the OMAP3/4/5 errata documents.
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*/
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#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
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struct timer_regs {
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u32 ocp_cfg;
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u32 tidr;
@@ -192,52 +178,4 @@ u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
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#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
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/* register offsets with the write pending bit encoded */
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#define WPSHIFT 16
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#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
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| (WP_TCLR << WPSHIFT))
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#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
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| (WP_TCRR << WPSHIFT))
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
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| (WP_TTGR << WPSHIFT))
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#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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| (WP_TMAR << WPSHIFT))
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#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
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| (WP_TPIR << WPSHIFT))
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#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
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| (WP_TNIR << WPSHIFT))
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#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
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| (WP_TCVR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
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(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
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(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
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#endif /* __CLOCKSOURCE_DMTIMER_H */

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