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phy: amlogic: Add G12A Analog MIPI D-PHY driver
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY used to communicate with DSI panels. Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/amlogic/Kconfig

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@@ -37,6 +37,18 @@ config PHY_MESON_GXL_USB2
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GXL and GXM SoCs.
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If unsure, say N.
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config PHY_MESON_G12A_MIPI_DPHY_ANALOG
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tristate "Meson G12A MIPI Analog DPHY driver"
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default ARCH_MESON
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depends on OF && (ARCH_MESON || COMPILE_TEST)
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select GENERIC_PHY
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select MFD_SYSCON
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select GENERIC_PHY_MIPI_DPHY
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help
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Enable this to support the Meson MIPI Analog DPHY found in Meson G12A
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SoCs.
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If unsure, say N.
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config PHY_MESON_G12A_USB2
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tristate "Meson G12A USB2 PHY driver"
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default ARCH_MESON

‎drivers/phy/amlogic/Makefile

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@@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
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obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
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obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
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obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
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obj-$(CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG) += phy-meson-g12a-mipi-dphy-analog.o
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obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
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obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o
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obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o

‎drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Meson G12A MIPI DSI Analog PHY
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*
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* Copyright (C) 2018 Amlogic, Inc. All rights reserved
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* Copyright (C) 2022 BayLibre, SAS
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* Author: Neil Armstrong <[email protected]>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/phy/phy.h>
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#define HHI_MIPI_CNTL0 0x00
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#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
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#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
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#define HHI_MIPI_CNTL1 0x04
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#define HHI_MIPI_CNTL1_BANDGAP BIT(16)
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#define HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
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#define HHI_MIPI_CNTL2 0x08
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#define HHI_MIPI_CNTL2_DIF_TX_CTL1 GENMASK(31, 16)
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#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
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#define HHI_MIPI_CNTL2_DIF_TX_CTL0 GENMASK(10, 0)
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#define DSI_LANE_0 BIT(4)
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#define DSI_LANE_1 BIT(3)
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#define DSI_LANE_CLK BIT(2)
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#define DSI_LANE_2 BIT(1)
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#define DSI_LANE_3 BIT(0)
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struct phy_g12a_mipi_dphy_analog_priv {
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struct phy *phy;
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struct regmap *regmap;
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struct phy_configure_opts_mipi_dphy config;
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};
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static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
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if (ret)
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return ret;
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memcpy(&priv->config, opts, sizeof(priv->config));
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return 0;
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}
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static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
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{
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struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
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unsigned int reg;
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regmap_write(priv->regmap, HHI_MIPI_CNTL0,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
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regmap_write(priv->regmap, HHI_MIPI_CNTL1,
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
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HHI_MIPI_CNTL1_BANDGAP);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2,
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
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FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
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reg = DSI_LANE_CLK;
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switch (priv->config.lanes) {
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case 4:
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reg |= DSI_LANE_3;
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fallthrough;
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case 3:
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reg |= DSI_LANE_2;
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fallthrough;
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case 2:
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reg |= DSI_LANE_1;
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fallthrough;
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case 1:
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reg |= DSI_LANE_0;
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break;
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default:
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reg = 0;
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}
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
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HHI_MIPI_CNTL2_CH_EN,
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FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
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return 0;
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}
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static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
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{
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struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
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regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
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regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
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return 0;
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}
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static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
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.configure = phy_g12a_mipi_dphy_analog_configure,
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.power_on = phy_g12a_mipi_dphy_analog_power_on,
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.power_off = phy_g12a_mipi_dphy_analog_power_off,
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.owner = THIS_MODULE,
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};
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static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy;
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struct device *dev = &pdev->dev;
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struct phy_g12a_mipi_dphy_analog_priv *priv;
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struct device_node *np = dev->of_node, *parent_np;
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struct regmap *map;
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priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Get the hhi system controller node */
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parent_np = of_get_parent(np);
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map = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(map))
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return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
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priv->regmap = map;
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priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
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if (IS_ERR(priv->phy))
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return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
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phy_set_drvdata(priv->phy, priv);
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dev_set_drvdata(dev, priv);
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phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy);
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}
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static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
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{
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.compatible = "amlogic,g12a-mipi-dphy-analog",
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
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static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
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.probe = phy_g12a_mipi_dphy_analog_probe,
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.driver = {
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.name = "phy-meson-g12a-mipi-dphy-analog",
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.of_match_table = phy_g12a_mipi_dphy_analog_of_match,
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},
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};
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module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
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MODULE_AUTHOR("Neil Armstrong <[email protected]>");
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MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
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MODULE_LICENSE("GPL v2");

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