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robimarkovinodkoul
robimarko
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vinodkoul
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phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, so add the support for the Gen3 one. It uses the same register layout as IPQ6018. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -450,6 +450,133 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
450450
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
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QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
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QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
502+
QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
504+
QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
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QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
509+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
510+
QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
511+
};
512+
513+
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
514+
QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
518+
};
519+
520+
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
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QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
529+
QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
541+
QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
551+
};
552+
553+
static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
554+
QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
555+
QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
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QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
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QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
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QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
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QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
560+
QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
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QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
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QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
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QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
564+
QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
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QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
566+
QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
567+
QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
568+
QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
569+
QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
570+
QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
571+
QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
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QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
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QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
574+
QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
575+
QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
576+
QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
577+
QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
578+
};
579+
453580
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
454581
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
455582
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -1424,6 +1551,36 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
14241551
.pwrdn_delay_max = 1005, /* us */
14251552
};
14261553

1554+
static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
1555+
.type = PHY_TYPE_PCIE,
1556+
.nlanes = 1,
1557+
1558+
.serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
1559+
.serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
1560+
.tx_tbl = ipq8074_pcie_gen3_tx_tbl,
1561+
.tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
1562+
.rx_tbl = ipq8074_pcie_gen3_rx_tbl,
1563+
.rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
1564+
.pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
1565+
.pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
1566+
.clk_list = ipq8074_pciephy_clk_l,
1567+
.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1568+
.reset_list = ipq8074_pciephy_reset_l,
1569+
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1570+
.vreg_list = NULL,
1571+
.num_vregs = 0,
1572+
.regs = ipq_pciephy_gen3_regs_layout,
1573+
1574+
.start_ctrl = SERDES_START | PCS_START,
1575+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1576+
1577+
.has_pwrdn_delay = true,
1578+
.pwrdn_delay_min = 995, /* us */
1579+
.pwrdn_delay_max = 1005, /* us */
1580+
1581+
.pipe_clock_rate = 250000000,
1582+
};
1583+
14271584
static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
14281585
.type = PHY_TYPE_PCIE,
14291586
.nlanes = 1,
@@ -2250,6 +2407,9 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = {
22502407
}, {
22512408
.compatible = "qcom,ipq8074-qmp-pcie-phy",
22522409
.data = &ipq8074_pciephy_cfg,
2410+
}, {
2411+
.compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
2412+
.data = &ipq8074_pciephy_gen3_cfg,
22532413
}, {
22542414
.compatible = "qcom,ipq6018-qmp-pcie-phy",
22552415
.data = &ipq6018_pciephy_cfg,

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