Skip to content

Commit 512dd35

Browse files
Alex Elderkuba-moo
Alex Elder
authored and
kuba-moo
committed
net: ipa: fix a surprising number of bad offsets
A recent commit eliminated a hack that adjusted the offset used for many GSI registers. It became possible because we now specify all GSI register offsets explicitly for every version of IPA. Unfortunately, a large number of register offsets were *not* updated as they should have been in that commit. For IPA v4.5+, the offset for every GSI register *except* the two inter-EE interrupt masking registers were supposed to have been reduced by 0xd000. Tested-by: Luca Weiss <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> # SM8350-HDK Fixes: 59b12b1 ("net: ipa: kill gsi->virt_raw") Signed-off-by: Alex Elder <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
1 parent 0b086d7 commit 512dd35

File tree

2 files changed

+50
-50
lines changed

2 files changed

+50
-50
lines changed

‎drivers/net/ipa/reg/gsi_reg-v4.5.c

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -137,33 +137,33 @@ REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
137137
0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
138138

139139
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
140-
0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
140+
0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
141141

142142
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
143-
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
143+
0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
144144

145145
static const u32 reg_gsi_status_fmask[] = {
146146
[ENABLED] = BIT(0),
147147
/* Bits 1-31 reserved */
148148
};
149149

150-
REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
150+
REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
151151

152152
static const u32 reg_ch_cmd_fmask[] = {
153153
[CH_CHID] = GENMASK(7, 0),
154154
/* Bits 8-23 reserved */
155155
[CH_OPCODE] = GENMASK(31, 24),
156156
};
157157

158-
REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
158+
REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
159159

160160
static const u32 reg_ev_ch_cmd_fmask[] = {
161161
[EV_CHID] = GENMASK(7, 0),
162162
/* Bits 8-23 reserved */
163163
[EV_OPCODE] = GENMASK(31, 24),
164164
};
165165

166-
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
166+
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
167167

168168
static const u32 reg_generic_cmd_fmask[] = {
169169
[GENERIC_OPCODE] = GENMASK(4, 0),
@@ -172,7 +172,7 @@ static const u32 reg_generic_cmd_fmask[] = {
172172
/* Bits 14-31 reserved */
173173
};
174174

175-
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
175+
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
176176

177177
static const u32 reg_hw_param_2_fmask[] = {
178178
[IRAM_SIZE] = GENMASK(2, 0),
@@ -188,58 +188,58 @@ static const u32 reg_hw_param_2_fmask[] = {
188188
[GSI_USE_INTER_EE] = BIT(31),
189189
};
190190

191-
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
191+
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
192192

193-
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
193+
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
194194

195-
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
195+
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
196196

197-
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
197+
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
198198

199-
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
199+
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
200200

201201
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
202-
0x0001f098 + 0x4000 * GSI_EE_AP);
202+
0x00012098 + 0x4000 * GSI_EE_AP);
203203

204204
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
205-
0x0001f09c + 0x4000 * GSI_EE_AP);
205+
0x0001209c + 0x4000 * GSI_EE_AP);
206206

207207
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
208-
0x0001f0a0 + 0x4000 * GSI_EE_AP);
208+
0x000120a0 + 0x4000 * GSI_EE_AP);
209209

210210
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
211-
0x0001f0a4 + 0x4000 * GSI_EE_AP);
211+
0x000120a4 + 0x4000 * GSI_EE_AP);
212212

213-
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
213+
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
214214

215215
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
216-
0x0001f0b8 + 0x4000 * GSI_EE_AP);
216+
0x000120b8 + 0x4000 * GSI_EE_AP);
217217

218218
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
219-
0x0001f0c0 + 0x4000 * GSI_EE_AP);
219+
0x000120c0 + 0x4000 * GSI_EE_AP);
220220

221-
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
221+
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
222222

223-
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
223+
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
224224

225-
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
225+
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
226226

227-
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
227+
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
228228

229-
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
229+
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
230230

231-
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
231+
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
232232

233233
static const u32 reg_cntxt_intset_fmask[] = {
234234
[INTYPE] = BIT(0)
235235
/* Bits 1-31 reserved */
236236
};
237237

238-
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
238+
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
239239

240-
REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
240+
REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
241241

242-
REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
242+
REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
243243

244244
static const u32 reg_cntxt_scratch_0_fmask[] = {
245245
[INTER_EE_RESULT] = GENMASK(2, 0),
@@ -248,7 +248,7 @@ static const u32 reg_cntxt_scratch_0_fmask[] = {
248248
/* Bits 8-31 reserved */
249249
};
250250

251-
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
251+
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
252252

253253
static const struct reg *reg_array[] = {
254254
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,

‎drivers/net/ipa/reg/gsi_reg-v4.9.c

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -27,19 +27,19 @@ static const u32 reg_ch_c_cntxt_0_fmask[] = {
2727
};
2828

2929
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30-
0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
30+
0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
3131

3232
static const u32 reg_ch_c_cntxt_1_fmask[] = {
3333
[CH_R_LENGTH] = GENMASK(19, 0),
3434
/* Bits 20-31 reserved */
3535
};
3636

3737
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38-
0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
38+
0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
3939

40-
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
40+
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
4141

42-
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
42+
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
4343

4444
static const u32 reg_ch_c_qos_fmask[] = {
4545
[WRR_WEIGHT] = GENMASK(3, 0),
@@ -53,7 +53,7 @@ static const u32 reg_ch_c_qos_fmask[] = {
5353
/* Bits 25-31 reserved */
5454
};
5555

56-
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
56+
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
5757

5858
static const u32 reg_error_log_fmask[] = {
5959
[ERR_ARG3] = GENMASK(3, 0),
@@ -67,16 +67,16 @@ static const u32 reg_error_log_fmask[] = {
6767
};
6868

6969
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
70-
0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
70+
0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
7171

7272
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
73-
0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
73+
0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
7474

7575
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
76-
0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
76+
0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
7777

7878
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
79-
0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
79+
0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
8080

8181
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
8282
[EV_CHTYPE] = GENMASK(3, 0),
@@ -89,23 +89,23 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
8989
};
9090

9191
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
92-
0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
92+
0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
9393

9494
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
9595
[R_LENGTH] = GENMASK(15, 0),
9696
};
9797

9898
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
99-
0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
99+
0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
100100

101101
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
102-
0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
102+
0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
103103

104104
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
105-
0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
105+
0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
106106

107107
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
108-
0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
108+
0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
109109

110110
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
111111
[EV_MODT] = GENMASK(15, 0),
@@ -114,28 +114,28 @@ static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
114114
};
115115

116116
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
117-
0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
117+
0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
118118

119119
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
120-
0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
120+
0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
121121

122122
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
123-
0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
123+
0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
124124

125125
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
126-
0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
126+
0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
127127

128128
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
129-
0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
129+
0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
130130

131131
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
132-
0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
132+
0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
133133

134134
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
135-
0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
135+
0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
136136

137137
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
138-
0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
138+
0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
139139

140140
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
141141
0x00011000 + 0x4000 * GSI_EE_AP, 0x08);

0 commit comments

Comments
 (0)