|
33 | 33 | #include <linux/io.h>
|
34 | 34 | #include <linux/delay.h>
|
35 | 35 | #include <linux/usb/otg.h>
|
| 36 | +#include <linux/usb/ulpi.h> |
36 | 37 | #include <linux/i2c/twl.h>
|
37 | 38 | #include <linux/regulator/consumer.h>
|
38 | 39 | #include <linux/err.h>
|
|
41 | 42 |
|
42 | 43 | /* Register defines */
|
43 | 44 |
|
44 |
| -#define VENDOR_ID_LO 0x00 |
45 |
| -#define VENDOR_ID_HI 0x01 |
46 |
| -#define PRODUCT_ID_LO 0x02 |
47 |
| -#define PRODUCT_ID_HI 0x03 |
48 |
| - |
49 |
| -#define FUNC_CTRL 0x04 |
50 |
| -#define FUNC_CTRL_SET 0x05 |
51 |
| -#define FUNC_CTRL_CLR 0x06 |
52 |
| -#define FUNC_CTRL_SUSPENDM (1 << 6) |
53 |
| -#define FUNC_CTRL_RESET (1 << 5) |
54 |
| -#define FUNC_CTRL_OPMODE_MASK (3 << 3) /* bits 3 and 4 */ |
55 |
| -#define FUNC_CTRL_OPMODE_NORMAL (0 << 3) |
56 |
| -#define FUNC_CTRL_OPMODE_NONDRIVING (1 << 3) |
57 |
| -#define FUNC_CTRL_OPMODE_DISABLE_BIT_NRZI (2 << 3) |
58 |
| -#define FUNC_CTRL_TERMSELECT (1 << 2) |
59 |
| -#define FUNC_CTRL_XCVRSELECT_MASK (3 << 0) /* bits 0 and 1 */ |
60 |
| -#define FUNC_CTRL_XCVRSELECT_HS (0 << 0) |
61 |
| -#define FUNC_CTRL_XCVRSELECT_FS (1 << 0) |
62 |
| -#define FUNC_CTRL_XCVRSELECT_LS (2 << 0) |
63 |
| -#define FUNC_CTRL_XCVRSELECT_FS4LS (3 << 0) |
64 |
| - |
65 |
| -#define IFC_CTRL 0x07 |
66 |
| -#define IFC_CTRL_SET 0x08 |
67 |
| -#define IFC_CTRL_CLR 0x09 |
68 |
| -#define IFC_CTRL_INTERFACE_PROTECT_DISABLE (1 << 7) |
69 |
| -#define IFC_CTRL_AUTORESUME (1 << 4) |
70 |
| -#define IFC_CTRL_CLOCKSUSPENDM (1 << 3) |
71 |
| -#define IFC_CTRL_CARKITMODE (1 << 2) |
72 |
| -#define IFC_CTRL_FSLSSERIALMODE_3PIN (1 << 1) |
73 |
| - |
74 |
| -#define TWL4030_OTG_CTRL 0x0A |
75 |
| -#define TWL4030_OTG_CTRL_SET 0x0B |
76 |
| -#define TWL4030_OTG_CTRL_CLR 0x0C |
77 |
| -#define TWL4030_OTG_CTRL_DRVVBUS (1 << 5) |
78 |
| -#define TWL4030_OTG_CTRL_CHRGVBUS (1 << 4) |
79 |
| -#define TWL4030_OTG_CTRL_DISCHRGVBUS (1 << 3) |
80 |
| -#define TWL4030_OTG_CTRL_DMPULLDOWN (1 << 2) |
81 |
| -#define TWL4030_OTG_CTRL_DPPULLDOWN (1 << 1) |
82 |
| -#define TWL4030_OTG_CTRL_IDPULLUP (1 << 0) |
83 |
| - |
84 |
| -#define USB_INT_EN_RISE 0x0D |
85 |
| -#define USB_INT_EN_RISE_SET 0x0E |
86 |
| -#define USB_INT_EN_RISE_CLR 0x0F |
87 |
| -#define USB_INT_EN_FALL 0x10 |
88 |
| -#define USB_INT_EN_FALL_SET 0x11 |
89 |
| -#define USB_INT_EN_FALL_CLR 0x12 |
90 |
| -#define USB_INT_STS 0x13 |
91 |
| -#define USB_INT_LATCH 0x14 |
92 |
| -#define USB_INT_IDGND (1 << 4) |
93 |
| -#define USB_INT_SESSEND (1 << 3) |
94 |
| -#define USB_INT_SESSVALID (1 << 2) |
95 |
| -#define USB_INT_VBUSVALID (1 << 1) |
96 |
| -#define USB_INT_HOSTDISCONNECT (1 << 0) |
97 |
| - |
98 |
| -#define CARKIT_CTRL 0x19 |
99 |
| -#define CARKIT_CTRL_SET 0x1A |
100 |
| -#define CARKIT_CTRL_CLR 0x1B |
101 |
| -#define CARKIT_CTRL_MICEN (1 << 6) |
102 |
| -#define CARKIT_CTRL_SPKRIGHTEN (1 << 5) |
103 |
| -#define CARKIT_CTRL_SPKLEFTEN (1 << 4) |
104 |
| -#define CARKIT_CTRL_RXDEN (1 << 3) |
105 |
| -#define CARKIT_CTRL_TXDEN (1 << 2) |
106 |
| -#define CARKIT_CTRL_IDGNDDRV (1 << 1) |
107 |
| -#define CARKIT_CTRL_CARKITPWR (1 << 0) |
108 |
| -#define CARKIT_PLS_CTRL 0x22 |
109 |
| -#define CARKIT_PLS_CTRL_SET 0x23 |
110 |
| -#define CARKIT_PLS_CTRL_CLR 0x24 |
111 |
| -#define CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3) |
112 |
| -#define CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2) |
113 |
| -#define CARKIT_PLS_CTRL_RXPLSEN (1 << 1) |
114 |
| -#define CARKIT_PLS_CTRL_TXPLSEN (1 << 0) |
115 |
| - |
116 | 45 | #define MCPC_CTRL 0x30
|
117 |
| -#define MCPC_CTRL_SET 0x31 |
118 |
| -#define MCPC_CTRL_CLR 0x32 |
119 | 46 | #define MCPC_CTRL_RTSOL (1 << 7)
|
120 | 47 | #define MCPC_CTRL_EXTSWR (1 << 6)
|
121 | 48 | #define MCPC_CTRL_EXTSWC (1 << 5)
|
|
125 | 52 | #define MCPC_CTRL_HS_UART (1 << 0)
|
126 | 53 |
|
127 | 54 | #define MCPC_IO_CTRL 0x33
|
128 |
| -#define MCPC_IO_CTRL_SET 0x34 |
129 |
| -#define MCPC_IO_CTRL_CLR 0x35 |
130 | 55 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
|
131 | 56 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
|
132 | 57 | #define MCPC_IO_CTRL_RXD_PU (1 << 3)
|
|
135 | 60 | #define MCPC_IO_CTRL_RTSTYP (1 << 0)
|
136 | 61 |
|
137 | 62 | #define MCPC_CTRL2 0x36
|
138 |
| -#define MCPC_CTRL2_SET 0x37 |
139 |
| -#define MCPC_CTRL2_CLR 0x38 |
140 | 63 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
|
141 | 64 |
|
142 | 65 | #define OTHER_FUNC_CTRL 0x80
|
143 |
| -#define OTHER_FUNC_CTRL_SET 0x81 |
144 |
| -#define OTHER_FUNC_CTRL_CLR 0x82 |
145 | 66 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
|
146 | 67 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
|
147 | 68 |
|
148 | 69 | #define OTHER_IFC_CTRL 0x83
|
149 |
| -#define OTHER_IFC_CTRL_SET 0x84 |
150 |
| -#define OTHER_IFC_CTRL_CLR 0x85 |
151 | 70 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
|
152 | 71 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
|
153 | 72 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
|
|
156 | 75 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
|
157 | 76 |
|
158 | 77 | #define OTHER_INT_EN_RISE 0x86
|
159 |
| -#define OTHER_INT_EN_RISE_SET 0x87 |
160 |
| -#define OTHER_INT_EN_RISE_CLR 0x88 |
161 | 78 | #define OTHER_INT_EN_FALL 0x89
|
162 |
| -#define OTHER_INT_EN_FALL_SET 0x8A |
163 |
| -#define OTHER_INT_EN_FALL_CLR 0x8B |
164 | 79 | #define OTHER_INT_STS 0x8C
|
165 | 80 | #define OTHER_INT_LATCH 0x8D
|
166 | 81 | #define OTHER_INT_VB_SESS_VLD (1 << 7)
|
|
178 | 93 | #define ID_RES_GND (1 << 0)
|
179 | 94 |
|
180 | 95 | #define POWER_CTRL 0xAC
|
181 |
| -#define POWER_CTRL_SET 0xAD |
182 |
| -#define POWER_CTRL_CLR 0xAE |
183 | 96 | #define POWER_CTRL_OTG_ENAB (1 << 5)
|
184 | 97 |
|
185 | 98 | #define OTHER_IFC_CTRL2 0xAF
|
186 |
| -#define OTHER_IFC_CTRL2_SET 0xB0 |
187 |
| -#define OTHER_IFC_CTRL2_CLR 0xB1 |
188 | 99 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
|
189 | 100 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
|
190 | 101 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
|
|
193 | 104 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
|
194 | 105 |
|
195 | 106 | #define REG_CTRL_EN 0xB2
|
196 |
| -#define REG_CTRL_EN_SET 0xB3 |
197 |
| -#define REG_CTRL_EN_CLR 0xB4 |
198 | 107 | #define REG_CTRL_ERROR 0xB5
|
199 | 108 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
|
200 | 109 |
|
201 | 110 | #define OTHER_FUNC_CTRL2 0xB8
|
202 |
| -#define OTHER_FUNC_CTRL2_SET 0xB9 |
203 |
| -#define OTHER_FUNC_CTRL2_CLR 0xBA |
204 | 111 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
|
205 | 112 |
|
206 | 113 | /* following registers do not have separate _clr and _set registers */
|
@@ -328,13 +235,13 @@ static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
|
328 | 235 | static inline int
|
329 | 236 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
|
330 | 237 | {
|
331 |
| - return twl4030_usb_write(twl, reg + 1, bits); |
| 238 | + return twl4030_usb_write(twl, ULPI_SET(reg), bits); |
332 | 239 | }
|
333 | 240 |
|
334 | 241 | static inline int
|
335 | 242 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
|
336 | 243 | {
|
337 |
| - return twl4030_usb_write(twl, reg + 2, bits); |
| 244 | + return twl4030_usb_write(twl, ULPI_CLR(reg), bits); |
338 | 245 | }
|
339 | 246 |
|
340 | 247 | /*-------------------------------------------------------------------------*/
|
@@ -393,11 +300,12 @@ static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
|
393 | 300 |
|
394 | 301 | switch (mode) {
|
395 | 302 | case T2_USB_MODE_ULPI:
|
396 |
| - twl4030_usb_clear_bits(twl, IFC_CTRL, IFC_CTRL_CARKITMODE); |
| 303 | + twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, |
| 304 | + ULPI_IFC_CTRL_CARKITMODE); |
397 | 305 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
|
398 |
| - twl4030_usb_clear_bits(twl, FUNC_CTRL, |
399 |
| - FUNC_CTRL_XCVRSELECT_MASK | |
400 |
| - FUNC_CTRL_OPMODE_MASK); |
| 306 | + twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, |
| 307 | + ULPI_FUNC_CTRL_XCVRSEL_MASK | |
| 308 | + ULPI_FUNC_CTRL_OPMODE_MASK); |
401 | 309 | break;
|
402 | 310 | case -1:
|
403 | 311 | /* FIXME: power on defaults */
|
|
0 commit comments