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| 1 | +SiFive FU540 PRCI bindings |
| 2 | + |
| 3 | +On the FU540 family of SoCs, most system-wide clock and reset integration |
| 4 | +is via the PRCI IP block. |
| 5 | + |
| 6 | +Required properties: |
| 7 | +- compatible: Should be "sifive,<chip>-prci". Only one value is |
| 8 | + supported: "sifive,fu540-c000-prci" |
| 9 | +- reg: Should describe the PRCI's register target physical address region |
| 10 | +- clocks: Should point to the hfclk device tree node and the rtcclk |
| 11 | + device tree node. The RTC clock here is not a time-of-day clock, |
| 12 | + but is instead a high-stability clock source for system timers |
| 13 | + and cycle counters. |
| 14 | +- #clock-cells: Should be <1> |
| 15 | + |
| 16 | +The clock consumer should specify the desired clock via the clock ID |
| 17 | +macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. |
| 18 | +These macros begin with PRCI_CLK_. |
| 19 | + |
| 20 | +The hfclk and rtcclk nodes are required, and represent physical |
| 21 | +crystals or resonators located on the PCB. These nodes should be present |
| 22 | +underneath /, rather than /soc. |
| 23 | + |
| 24 | +Examples: |
| 25 | + |
| 26 | +/* under /, in PCB-specific DT data */ |
| 27 | +hfclk: hfclk { |
| 28 | + #clock-cells = <0>; |
| 29 | + compatible = "fixed-clock"; |
| 30 | + clock-frequency = <33333333>; |
| 31 | + clock-output-names = "hfclk"; |
| 32 | +}; |
| 33 | +rtcclk: rtcclk { |
| 34 | + #clock-cells = <0>; |
| 35 | + compatible = "fixed-clock"; |
| 36 | + clock-frequency = <1000000>; |
| 37 | + clock-output-names = "rtcclk"; |
| 38 | +}; |
| 39 | + |
| 40 | +/* under /soc, in SoC-specific DT data */ |
| 41 | +prci: clock-controller@10000000 { |
| 42 | + compatible = "sifive,fu540-c000-prci"; |
| 43 | + reg = <0x0 0x10000000 0x0 0x1000>; |
| 44 | + clocks = <&hfclk>, <&rtcclk>; |
| 45 | + #clock-cells = <1>; |
| 46 | +}; |
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