@@ -124,17 +124,12 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
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u16 core = 0 ; /* FIXME */
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u32 val , offset = core << 4 ;
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dma_addr_t dma_addr ;
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- void * addr ;
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int ret ;
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- addr = kmemdup (p , size , GFP_ATOMIC );
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- if (!addr )
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- return - ENOMEM ;
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-
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- dma_addr = dma_map_single (npu -> dev , addr , size , DMA_TO_DEVICE );
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+ dma_addr = dma_map_single (npu -> dev , p , size , DMA_TO_DEVICE );
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ret = dma_mapping_error (npu -> dev , dma_addr );
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if (ret )
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- goto out ;
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+ return ret ;
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spin_lock_bh (& npu -> cores [core ].lock );
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@@ -155,8 +150,6 @@ static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id,
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spin_unlock_bh (& npu -> cores [core ].lock );
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dma_unmap_single (npu -> dev , dma_addr , size , DMA_TO_DEVICE );
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- out :
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- kfree (addr );
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return ret ;
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}
@@ -261,76 +254,101 @@ static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance)
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static int airoha_npu_ppe_init (struct airoha_npu * npu )
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{
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- struct ppe_mbox_data ppe_data = {
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- .func_type = NPU_OP_SET ,
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- .func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT ,
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- .init_info = {
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- .ppe_type = PPE_TYPE_L2B_IPV4_IPV6 ,
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- .wan_mode = QDMA_WAN_ETHER ,
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- },
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- };
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+ struct ppe_mbox_data * ppe_data ;
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+ int err ;
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+
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+ ppe_data = kzalloc (sizeof (* ppe_data ), GFP_KERNEL );
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+ if (!ppe_data )
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+ return - ENOMEM ;
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- return airoha_npu_send_msg (npu , NPU_FUNC_PPE , & ppe_data ,
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- sizeof (struct ppe_mbox_data ));
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+ ppe_data -> func_type = NPU_OP_SET ;
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+ ppe_data -> func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT ;
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+ ppe_data -> init_info .ppe_type = PPE_TYPE_L2B_IPV4_IPV6 ;
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+ ppe_data -> init_info .wan_mode = QDMA_WAN_ETHER ;
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+
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+ err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , ppe_data ,
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+ sizeof (* ppe_data ));
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+ kfree (ppe_data );
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+
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+ return err ;
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}
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static int airoha_npu_ppe_deinit (struct airoha_npu * npu )
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{
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- struct ppe_mbox_data ppe_data = {
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- .func_type = NPU_OP_SET ,
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- .func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT ,
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- };
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+ struct ppe_mbox_data * ppe_data ;
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+ int err ;
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+
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+ ppe_data = kzalloc (sizeof (* ppe_data ), GFP_KERNEL );
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+ if (!ppe_data )
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+ return - ENOMEM ;
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+
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+ ppe_data -> func_type = NPU_OP_SET ;
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+ ppe_data -> func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT ;
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- return airoha_npu_send_msg (npu , NPU_FUNC_PPE , & ppe_data ,
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- sizeof (struct ppe_mbox_data ));
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+ err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , ppe_data ,
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+ sizeof (* ppe_data ));
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+ kfree (ppe_data );
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+
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+ return err ;
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}
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static int airoha_npu_ppe_flush_sram_entries (struct airoha_npu * npu ,
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dma_addr_t foe_addr ,
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int sram_num_entries )
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{
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- struct ppe_mbox_data ppe_data = {
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- .func_type = NPU_OP_SET ,
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- .func_id = PPE_FUNC_SET_WAIT_API ,
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- .set_info = {
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- .func_id = PPE_SRAM_RESET_VAL ,
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- .data = foe_addr ,
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- .size = sram_num_entries ,
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- },
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- };
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+ struct ppe_mbox_data * ppe_data ;
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+ int err ;
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+
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+ ppe_data = kzalloc (sizeof (* ppe_data ), GFP_KERNEL );
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+ if (!ppe_data )
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+ return - ENOMEM ;
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+
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+ ppe_data -> func_type = NPU_OP_SET ;
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+ ppe_data -> func_id = PPE_FUNC_SET_WAIT_API ;
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+ ppe_data -> set_info .func_id = PPE_SRAM_RESET_VAL ;
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+ ppe_data -> set_info .data = foe_addr ;
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+ ppe_data -> set_info .size = sram_num_entries ;
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+
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+ err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , ppe_data ,
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+ sizeof (* ppe_data ));
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+ kfree (ppe_data );
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- return airoha_npu_send_msg (npu , NPU_FUNC_PPE , & ppe_data ,
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- sizeof (struct ppe_mbox_data ));
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+ return err ;
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}
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static int airoha_npu_foe_commit_entry (struct airoha_npu * npu ,
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dma_addr_t foe_addr ,
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u32 entry_size , u32 hash , bool ppe2 )
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{
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- struct ppe_mbox_data ppe_data = {
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- .func_type = NPU_OP_SET ,
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- .func_id = PPE_FUNC_SET_WAIT_API ,
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- .set_info = {
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- .data = foe_addr ,
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- .size = entry_size ,
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- },
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- };
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+ struct ppe_mbox_data * ppe_data ;
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int err ;
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- ppe_data .set_info .func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
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- : PPE_SRAM_SET_ENTRY ;
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+ ppe_data = kzalloc (sizeof (* ppe_data ), GFP_ATOMIC );
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+ if (!ppe_data )
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+ return - ENOMEM ;
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+
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+ ppe_data -> func_type = NPU_OP_SET ;
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+ ppe_data -> func_id = PPE_FUNC_SET_WAIT_API ;
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+ ppe_data -> set_info .data = foe_addr ;
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+ ppe_data -> set_info .size = entry_size ;
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+ ppe_data -> set_info .func_id = ppe2 ? PPE2_SRAM_SET_ENTRY
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+ : PPE_SRAM_SET_ENTRY ;
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- err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , & ppe_data ,
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- sizeof (struct ppe_mbox_data ));
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+ err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , ppe_data ,
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+ sizeof (* ppe_data ));
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if (err )
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- return err ;
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+ goto out ;
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+
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+ ppe_data -> set_info .func_id = PPE_SRAM_SET_VAL ;
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+ ppe_data -> set_info .data = hash ;
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+ ppe_data -> set_info .size = sizeof (u32 );
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- ppe_data .set_info .func_id = PPE_SRAM_SET_VAL ;
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- ppe_data .set_info .data = hash ;
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- ppe_data .set_info .size = sizeof (u32 );
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+ err = airoha_npu_send_msg (npu , NPU_FUNC_PPE , ppe_data ,
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+ sizeof (* ppe_data ));
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+ out :
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+ kfree (ppe_data );
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- return airoha_npu_send_msg (npu , NPU_FUNC_PPE , & ppe_data ,
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- sizeof (struct ppe_mbox_data ));
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+ return err ;
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}
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struct airoha_npu * airoha_npu_get (struct device * dev )
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